cpu.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

      end if;
    end if;

  end process;

  unxxx246_in <= A_WE_StdLogicVector ((commit = '1'),instruction_delay,A_WE_StdLogicVector (true,Std_Logic_Vector'(A_ToStdLogicVector('1') & unxxx246_out(2 DOWNTO 1)),unxxx246_out));
  wait_counter_output <= unxxx246_out(0);

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity cpu_subinstruction_unit is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal commit : IN STD_LOGIC;
                 signal d1_instruction_fifo_out : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
                 signal feed_new_instruction : IN STD_LOGIC;
                 signal force_trap_acknowledge : IN STD_LOGIC;
                 signal is_cancelled : IN STD_LOGIC;
                 signal is_neutrino : IN STD_LOGIC;
                 signal pipe_run : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal is_subinstruction : OUT STD_LOGIC;
                 signal subinstruction : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
              );

end entity cpu_subinstruction_unit;


architecture europa of cpu_subinstruction_unit is
              signal internal_is_subinstruction1 :  STD_LOGIC;
              signal internal_subinstruction2 :  STD_LOGIC_VECTOR (5 DOWNTO 0);
              signal local_pipe_clk_en :  STD_LOGIC;
              signal p1_subinstruction :  STD_LOGIC_VECTOR (5 DOWNTO 0);
              signal p1_subinstruction_load_value :  STD_LOGIC_VECTOR (5 DOWNTO 0);
              signal pipe_state_we :  STD_LOGIC;
              signal subcount_en :  STD_LOGIC;

begin

  local_pipe_clk_en <= commit;
  pipe_state_we <= local_pipe_clk_en AND NOT is_neutrino AND NOT is_cancelled;
  subcount_en <= feed_new_instruction AND pipe_run;
  --subinstruction_counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_subinstruction2 <= "000000";
    elsif clk'event and clk = '1' then
      if subcount_en = '1' then 
        internal_subinstruction2 <= p1_subinstruction;
      end if;
    end if;

  end process;

  p1_subinstruction <= A_WE_StdLogicVector ((internal_is_subinstruction1 = '1'),(internal_subinstruction2 - "000001"),p1_subinstruction_load_value);
  p1_subinstruction_load_value <= A_WE_StdLogicVector ((d1_instruction_fifo_read_data_bad = '1'),"000000",A_WE_StdLogicVector ((force_trap_acknowledge = '1'),"000011",A_WE_StdLogicVector (((((NOT d1_instruction_fifo_out(15) AND NOT d1_instruction_fifo_out(14) AND NOT d1_instruction_fifo_out(13) AND d1_instruction_fifo_out(12) AND d1_instruction_fifo_out(11) AND NOT d1_instruction_fifo_out(10)))) = '1'),"000001",A_WE_StdLogicVector (((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14) AND d1_instruction_fifo_out(13) AND d1_instruction_fifo_out(12) AND d1_instruction_fifo_out(11) AND NOT d1_instruction_fifo_out(10)) AND NOT d1_instruction_fifo_out(9) AND d1_instruction_fifo_out(8))))) = '1'),"000011",A_WE_StdLogicVector (((((NOT d1_instruction_fifo_out(15) AND NOT d1_instruction_fifo_out(14) AND NOT d1_instruction_fifo_out(13) AND d1_instruction_fifo_out(12) AND d1_instruction_fifo_out(11) AND d1_instruction_fifo_out(10)))) = '1'),"000001",A_WE_StdLogicVector (((((NOT d1_instruction_fifo_out(15) AND NOT d1_instruction_fifo_out(14) AND d1_instruction_fifo_out(13) AND NOT d1_instruction_fifo_out(12) AND NOT d1_instruction_fifo_out(11) AND NOT d1_instruction_fifo_out(10)))) = '1'),"000001",A_WE_StdLogicVector (((((NOT d1_instruction_fifo_out(15) AND NOT d1_instruction_fifo_out(14) AND d1_instruction_fifo_out(13) AND NOT d1_instruction_fifo_out(12) AND NOT d1_instruction_fifo_out(11) AND d1_instruction_fifo_out(10)))) = '1'),"000001",A_WE_StdLogicVector (((((NOT d1_instruction_fifo_out(15) AND NOT d1_instruction_fifo_out(14) AND d1_instruction_fifo_out(13) AND NOT d1_instruction_fifo_out(12) AND d1_instruction_fifo_out(11) AND NOT d1_instruction_fifo_out(10)))) = '1'),"000001",A_WE_StdLogicVector (((((NOT d1_instruction_fifo_out(15) AND NOT d1_instruction_fifo_out(14) AND d1_instruction_fifo_out(13) AND NOT d1_instruction_fifo_out(12) AND d1_instruction_fifo_out(11) AND d1_instruction_fifo_out(10)))) = '1'),"000001",A_WE_StdLogicVector (((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14) AND d1_instruction_fifo_out(13) AND d1_instruction_fifo_out(12) AND d1_instruction_fifo_out(11) AND d1_instruction_fifo_out(10)) AND NOT d1_instruction_fifo_out(9) AND NOT d1_instruction_fifo_out(8) AND d1_instruction_fifo_out(7) AND NOT d1_instruction_fifo_out(6) AND d1_instruction_fifo_out(5))))) = '1'),"000001",A_WE_StdLogicVector (((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14) AND d1_instruction_fifo_out(13) AND d1_instruction_fifo_out(12) AND d1_instruction_fifo_out(11) AND d1_instruction_fifo_out(10)) AND NOT d1_instruction_fifo_out(9) AND NOT d1_instruction_fifo_out(8) AND d1_instruction_fifo_out(7) AND d1_instruction_fifo_out(6) AND NOT d1_instruction_fifo_out(5))))) = '1'),"000001",A_WE_StdLogicVector (((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14) AND NOT d1_instruction_fifo_out(13) AND d1_instruction_fifo_out(12) AND NOT d1_instruction_fifo_out(11) AND NOT d1_instruction_fifo_out(10)))) = '1'),"000001",A_WE_StdLogicVector (((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14) AND NOT d1_instruction_fifo_out(13) AND d1_instruction_fifo_out(12) AND NOT d1_instruction_fifo_out(11) AND d1_instruction_fifo_out(10)))) = '1'),"000001",A_WE_StdLogicVector (((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14) AND d1_instruction_fifo_out(13) AND d1_instruction_fifo_out(12) AND NOT d1_instruction_fifo_out(11) AND NOT d1_instruction_fifo_out(10)))) = '1'),"100010",A_WE_StdLogicVector (((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14) AND d1_instruction_fifo_out(13) AND d1_instruction_fifo_out(12) AND d1_instruction_fifo_out(11) AND d1_instruction_fifo_out(10)) AND d1_instruction_fifo_out(9) AND NOT d1_instruction_fifo_out(8) AND d1_instruction_fifo_out(7) AND NOT d1_instruction_fifo_out(6) AND NOT d1_instruction_fifo_out(5))))) = '1'),"000001",A_WE_StdLogicVector (((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14) AND d1_instruction_fifo_out(13) AND d1_instruction_fifo_out(12) AND d1_instruction_fifo_out(11) AND d1_instruction_fifo_out(10)) AND d1_instruction_fifo_out(9) AND NOT d1_instruction_fifo_out(8) AND d1_instruction_fifo_out(7) AND NOT d1_instruction_fifo_out(6) AND d1_instruction_fifo_out(5))))) = '1'),"000010",A_WE_StdLogicVector (((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14) AND d1_instruction_fifo_out(13) AND d1_instruction_fifo_out(12) AND d1_instruction_fifo_out(11) AND d1_instruction_fifo_out(10)) AND d1_instruction_fifo_out(9) AND NOT d1_instruction_fifo_out(8) AND d1_instruction_fifo_out(7) AND d1_instruction_fifo_out(6) AND NOT d1_instruction_fifo_out(5))))) = '1'),"000001",A_WE_StdLogicVector (((((((NOT d1_instruction_fifo_out(15) AND d1_instruction_fifo_out(14) AND d1_instruction_fifo_out(13) AND d1_instruction_fifo_out(12) AND d1_instruction_fifo_out(11) AND d1_instruction_fifo_out(10)) AND d1_instruction_fifo_out(9) AND d1_instruction_fifo_out(8) AND NOT d1_instruction_fifo_out(7) AND d1_instruction_fifo_out(6) AND NOT d1_instruction_fifo_out(5))))) = '1'),"000001","000000"))))))))))))))))));
  internal_is_subinstruction1 <= (or_reduce(internal_subinstruction2)) AND (NOT is_neutrino);
  --vhdl renameroo for output signals
  is_subinstruction <= internal_is_subinstruction1;
  --vhdl renameroo for output signals
  subinstruction <= internal_subinstruction2;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity cpu_instruction_scheduler is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal d1_instruction_fifo_out : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
                 signal do_cancel_next_instruction : IN STD_LOGIC;
                 signal do_force_trap : IN STD_LOGIC;
                 signal do_iPFX :  STD_LOGIC;
                 signal do_iSKPx : IN STD_LOGIC;
                 signal do_skip : IN STD_LOGIC;
                 signal force_trap_acknowledge : IN STD_LOGIC;
                 signal hold_for_hazard : IN STD_LOGIC;
                 signal is_cancelled : IN STD_LOGIC;
                 signal must_run_to_completion : IN STD_LOGIC;
                 signal op_jmpcall : IN STD_LOGIC;
                 signal op_save_restore : IN STD_LOGIC;
                 signal pipe_run : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal trap_if_restore : IN STD_LOGIC;
                 signal trap_if_save : IN STD_LOGIC;

              -- outputs:
                 signal commit : OUT STD_LOGIC;
                 signal feed_new_instruction : OUT STD_LOGIC;
                 signal is_cancelled_from_commit_stage : OUT STD_LOGIC;
                 signal is_neutrino : OUT STD_LOGIC;
                 signal is_subinstruction : OUT STD_LOGIC;
                 signal subinstruction : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
              );

end entity cpu_instruction_scheduler;


architecture europa of cpu_instruction_scheduler is
component cpu_wait_counter is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal commit : IN STD_LOGIC;
                    signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
                    signal do_force_trap : IN STD_LOGIC;
                    signal do_iSKPx :  STD_LOGIC;
                    signal hold_for_hazard : IN STD_LOGIC;
                    signal is_cancelled : IN STD_LOGIC;
                    signal is_neutrino : IN STD_LOGIC;
                    signal must_run_to_completion :  STD_LOGIC;
                    signal op_jmpcall :  STD_LOGIC;
                    signal op_save_restore :  STD_LOGIC;
                    signal pipe_run : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal subinstruction : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                    signal trap_if_restore : IN STD_LOGIC;
                    signal trap_if_save : IN STD_LOGIC;

                 -- outputs:
                    signal feed_new_instruction : OUT STD_LOGIC
                 );
end component cpu_wait_counter;

component cpu_subinstruction_unit is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal commit : IN STD_LOGIC;
                    signal d1_instruction_fifo_out : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
                    signal feed_new_instruction : IN STD_LOGIC;
                    signal force_trap_acknowledge : IN STD_LOGIC;
                    signal is_cancelled : IN STD_LOGIC;
                    signal is_neutrino : IN STD_LOGIC;
                    signal pipe_run : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;

                 -- outputs:
                    signal is_subinstruction : OUT STD_LOGIC;
                    signal subinstruction : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
                 );
end component cpu_subinstruction_unit;

              signal cancel_delay_slot_acknowledge :  STD_LOGIC;
              signal dont_forget_to_cancel_delay_slot :  STD_LOGIC;
              signal dont_forget_to_skip :  STD_LOGIC;
              signal instruction_not_ready :  STD_LOGIC;
              signal internal_commit1 :  STD_LOGIC;
              signal internal_feed_new_instruction :  STD_LOGIC;
              signal internal_is_neutrino1 :  STD_LOGIC;
              signal internal_is_subinstruction :  STD_LOGIC;
              signal internal_subinstruction1 :  STD_LOGIC_VECTOR (5 DOWNTO 0);
              signal local_pipe_clk_en :  STD_LOGIC;
              signal p1_is_neutrino :  STD_LOGIC;
              signal pipe_state_we :  STD_LOGIC;
              signal qualified_skip_request :  STD_LOGIC;
              signal skip_acknowledge :  STD_LOGIC;
              signal waiting_for_skip_outcome :  STD_LOGIC;

begin

  local_pipe_clk_en <= internal_commit1;
  pipe_state_we <= local_pipe_clk_en AND NOT internal_is_neutrino1 AND NOT is_cancelled;
  the_cpu_wait_counter : cpu_wait_counter
    port map(
      feed_new_instruction => internal_feed_new_instruction,
      is_neutrino => internal_is_neutrino1,
      do_force_trap => do_force_trap,
      hold_for_hazard => hold_for_hazard,
      d1_instruction_fifo_read_data_bad => d1_instruction_fifo_read_data_bad,
      commit => internal_commit1,
      trap_if_restore => trap_if_restore,
      clk => clk,
      op_jmpcall => op_jmpcall,
      op_save_restore => op_save_restore,
      is_cancelled => is_cancelled,
      pipe_run => pipe_run,
      trap_if_save => trap_if_save,
      do_iSKPx => do_iSKPx,
      reset_n => reset_n,
      subinstruction => internal_subinstruction1,
      must_run_to_completion => must_run_to_completion
    );


  the_cpu_subinstruction_unit : cpu_subinstruction_unit
    port map(
      is_subinstruction => internal_is_subinstruction,
      subinstruction => internal_subinstruction1,
      is_neutrino => internal_is_neutrino1,
      d1_instruction_fifo_read_data_bad => d1_instruction_fifo_read_data_bad,
      commit => internal_commit1,
      d1_instruction_fifo_out => d1_instruction_fifo_out,
      clk => clk,
      feed_new_instruction => internal_feed_new_instruction,
      is_cancelled => is_cancelled,
      pipe_run => pipe_run,
      reset_n => reset_n,
      force_trap_acknowledge => force_trap_acknowledge
    );


  internal_commit1 <= internal_feed_new_instruction AND (NOT internal_is_subinstruction) AND pipe_run;
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_is_neutrino1 <= '1';
    elsif clk'event and clk = '1' then
      if pipe_run = '1' then 
        internal_is_neutrino1 <= p1_is_neutrino;
      end if;
    end if;

  end process;

  p1_is_neutrino <= instruction_not_ready AND (NOT hold_for_hazard);
  instruction_