cpu.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity cpu_instruction_receive is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal commit : IN STD_LOGIC;
                 signal do_branch : IN STD_LOGIC;
                 signal do_force_trap : IN STD_LOGIC;
                 signal do_jump : IN STD_LOGIC;
                 signal feed_new_instruction : IN STD_LOGIC;
                 signal forced_trap_instruction : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal i_datavalid : IN STD_LOGIC;
                 signal i_readdata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal i_wait : IN STD_LOGIC;
                 signal is_subinstruction : IN STD_LOGIC;
                 signal p1_flush : IN STD_LOGIC;
                 signal pipe_freeze : IN STD_LOGIC;
                 signal pipe_run : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal target_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
                 signal trap_properly_received : IN STD_LOGIC;

              -- outputs:
                 signal d1_instruction_fifo_out : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal d1_instruction_fifo_read_data_bad : OUT STD_LOGIC;
                 signal force_trap_acknowledge : OUT STD_LOGIC;
                 signal i_read : OUT STD_LOGIC;
                 signal instruction : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal instruction_fifo_read_data_bad : OUT STD_LOGIC;
                 signal next_instruction_address : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
              );

attribute auto_dissolve : boolean ;
attribute auto_dissolve of cpu_instruction_receive : entity is FALSE ;
end entity cpu_instruction_receive;


architecture europa of cpu_instruction_receive is
component cpu_cpu_instruction_fifo_fifo_module is 
           port (
                 -- inputs:
                    signal clk :  STD_LOGIC;
                    signal clk_en :  STD_LOGIC;
                    signal fifo_read :  STD_LOGIC;
                    signal fifo_wr_data :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal fifo_write :  STD_LOGIC;
                    signal flush :  STD_LOGIC;
                    signal i_wait : IN STD_LOGIC;
                    signal reset_n :  STD_LOGIC;

                 -- outputs:
                    signal fifo_rd_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal fifo_read_data_bad : OUT STD_LOGIC;
                    signal i_read : OUT STD_LOGIC
                 );
end component cpu_cpu_instruction_fifo_fifo_module;

              signal dont_forget_to_force_trap :  STD_LOGIC;
              signal instruction_fifo_out :  STD_LOGIC_VECTOR (15 DOWNTO 0);
              signal instruction_fifo_read :  STD_LOGIC;
              signal internal_d1_instruction_fifo_out :  STD_LOGIC_VECTOR (15 DOWNTO 0);
              signal internal_d1_instruction_fifo_read_data_bad :  STD_LOGIC;
              signal internal_force_trap_acknowledge :  STD_LOGIC;
              signal internal_i_read3 :  STD_LOGIC;
              signal internal_instruction_fifo_read_data_bad :  STD_LOGIC;
              signal internal_next_instruction_address1 :  STD_LOGIC_VECTOR (19 DOWNTO 0);
              signal next_instruction_address_enable :  STD_LOGIC;
              signal p1_next_instruction_address :  STD_LOGIC_VECTOR (19 DOWNTO 0);
              signal use_saved_next_address :  STD_LOGIC;

begin

  the_cpu_cpu_instruction_fifo_fifo_module : cpu_cpu_instruction_fifo_fifo_module
    port map(
      i_read => internal_i_read3,
      fifo_rd_data => instruction_fifo_out,
      fifo_read_data_bad => internal_instruction_fifo_read_data_bad,
      fifo_wr_data => i_readdata,
      i_wait => i_wait,
      clk_en => '1',
      fifo_write => i_datavalid,
      flush => p1_flush,
      clk => clk,
      reset_n => reset_n,
      fifo_read => instruction_fifo_read
    );


  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_d1_instruction_fifo_read_data_bad <= '1';
    elsif clk'event and clk = '1' then
      if instruction_fifo_read = '1' then 
        internal_d1_instruction_fifo_read_data_bad <= internal_instruction_fifo_read_data_bad OR p1_flush;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_d1_instruction_fifo_out <= "0000000000000000";
    elsif clk'event and clk = '1' then
      if instruction_fifo_read = '1' then 
        internal_d1_instruction_fifo_out <= instruction_fifo_out;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      dont_forget_to_force_trap <= '0';
    elsif clk'event and clk = '1' then
      if pipe_run = '1' then 
        if trap_properly_received = '1' then 
          dont_forget_to_force_trap <= '0';
        elsif do_force_trap = '1' then 
          dont_forget_to_force_trap <= '1';
        end if;
      end if;
    end if;

  end process;

  internal_force_trap_acknowledge <= dont_forget_to_force_trap;
  instruction <= A_WE_StdLogicVector ((internal_force_trap_acknowledge = '1'),forced_trap_instruction,internal_d1_instruction_fifo_out);
  instruction_fifo_read <= commit OR ((internal_d1_instruction_fifo_read_data_bad AND NOT pipe_freeze));
  next_instruction_address_enable <= feed_new_instruction AND (NOT is_subinstruction) AND (NOT pipe_freeze) AND (NOT internal_d1_instruction_fifo_read_data_bad) AND (NOT internal_force_trap_acknowledge);
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_next_instruction_address1 <= "00000000000000000000";
    elsif clk'event and clk = '1' then
      if next_instruction_address_enable = '1' then 
        internal_next_instruction_address1 <= p1_next_instruction_address;
      end if;
    end if;

  end process;

  p1_next_instruction_address <= A_WE_StdLogicVector ((((((do_branch OR do_jump) OR use_saved_next_address))) = '1'),target_address,internal_next_instruction_address1 + "00000000000000000001");
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      use_saved_next_address <= '0';
    elsif clk'event and clk = '1' then
      if pipe_run = '1' then 
        if ((((((do_jump OR do_branch)) AND NOT next_instruction_address_enable)))) = '1' then 
          use_saved_next_address <= '1';
        elsif next_instruction_address_enable = '1' then 
          use_saved_next_address <= '0';
        end if;
      end if;
    end if;

  end process;

  --vhdl renameroo for output signals
  i_read <= internal_i_read3;
  --vhdl renameroo for output signals
  d1_instruction_fifo_read_data_bad <= internal_d1_instruction_fifo_read_data_bad;
  --vhdl renameroo for output signals
  d1_instruction_fifo_out <= internal_d1_instruction_fifo_out;
  --vhdl renameroo for output signals
  next_instruction_address <= internal_next_instruction_address1;
  --vhdl renameroo for output signals
  instruction_fifo_read_data_bad <= internal_instruction_fifo_read_data_bad;
  --vhdl renameroo for output signals
  force_trap_acknowledge <= internal_force_trap_acknowledge;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity cpu_wait_counter is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal commit : IN STD_LOGIC;
                 signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
                 signal do_force_trap : IN STD_LOGIC;
                 signal do_iSKPx :  STD_LOGIC;
                 signal hold_for_hazard : IN STD_LOGIC;
                 signal is_cancelled : IN STD_LOGIC;
                 signal is_neutrino : IN STD_LOGIC;
                 signal must_run_to_completion :  STD_LOGIC;
                 signal op_jmpcall :  STD_LOGIC;
                 signal op_save_restore :  STD_LOGIC;
                 signal pipe_run : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal subinstruction : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
                 signal trap_if_restore : IN STD_LOGIC;
                 signal trap_if_save : IN STD_LOGIC;

              -- outputs:
                 signal feed_new_instruction : OUT STD_LOGIC
              );

end entity cpu_wait_counter;


architecture europa of cpu_wait_counter is
              signal instruction_delay :  STD_LOGIC_VECTOR (2 DOWNTO 0);
              signal local_pipe_clk_en :  STD_LOGIC;
              signal pipe_state_we :  STD_LOGIC;
              signal unxxx246_in :  STD_LOGIC_VECTOR (2 DOWNTO 0);
              signal unxxx246_out :  STD_LOGIC_VECTOR (2 DOWNTO 0);
              signal wait_counter_output :  STD_LOGIC;
              signal wait_once_after :  STD_LOGIC;

begin

  local_pipe_clk_en <= commit;
  pipe_state_we <= local_pipe_clk_en AND NOT is_neutrino AND NOT is_cancelled;
  instruction_delay <= A_WE_StdLogicVector ((((((d1_instruction_fifo_read_data_bad AND commit)))) = '1'),"111",A_WE_StdLogicVector ((wait_once_after = '1'),"110",A_WE_StdLogicVector ((must_run_to_completion = '1'),"000","111")));
  wait_once_after <= op_jmpcall OR (op_save_restore AND (trap_if_save OR trap_if_restore OR NOT is_neutrino));
  feed_new_instruction <= (((wait_counter_output OR (or_reduce(subinstruction)))) AND (NOT hold_for_hazard)) AND (NOT do_force_trap);
  --wait_counter_shift_register_reg, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      unxxx246_out <= "000";
    elsif clk'event and clk = '1' then
      if ((((pipe_run AND (NOT or_reduce(subinstruction)) AND NOT hold_for_hazard)))) = '1' then 
        unxxx246_out <= unxxx246_in;