cpu.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

    );


  the_cpu_target_address : cpu_target_address
    port map(
      target_address => internal_target_address,
      jump_target_address => jump_target_address,
      do_branch => do_branch,
      clk => clk,
      signed_branch_offset => signed_branch_offset,
      do_jump => do_jump,
      branch_base => branch_base,
      pipe_run => pipe_run,
      reset_n => reset_n
    );


  i_address <= pc & A_ToStdLogicVector('0');
  --vhdl renameroo for output signals
  target_address <= internal_target_address;
  --vhdl renameroo for output signals
  i_flush <= internal_i_flush3;
  --vhdl renameroo for output signals
  p1_flush <= internal_p1_flush;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity cpu_cpu_instruction_fifo_fifo_module is 
        port (
              -- inputs:
                 signal clk :  STD_LOGIC;
                 signal clk_en :  STD_LOGIC;
                 signal fifo_read :  STD_LOGIC;
                 signal fifo_wr_data :  STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal fifo_write :  STD_LOGIC;
                 signal flush :  STD_LOGIC;
                 signal i_wait : IN STD_LOGIC;
                 signal reset_n :  STD_LOGIC;

              -- outputs:
                 signal fifo_rd_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal fifo_read_data_bad : OUT STD_LOGIC;
                 signal i_read : OUT STD_LOGIC
              );

end entity cpu_cpu_instruction_fifo_fifo_module;


architecture europa of cpu_cpu_instruction_fifo_fifo_module is
              signal bad_news :  STD_LOGIC;
              signal continue_read_cycle :  STD_LOGIC;
              signal dont_forget_to_reset_i_read :  STD_LOGIC;
              signal fifo_becoming_empty :  STD_LOGIC;
              signal fifo_dec :  STD_LOGIC;
              signal fifo_inc :  STD_LOGIC;
              signal fifo_reg_0 :  STD_LOGIC_VECTOR (15 DOWNTO 0);
              signal fifo_reg_0_read_select :  STD_LOGIC;
              signal fifo_reg_0_write_select :  STD_LOGIC;
              signal fifo_reg_1 :  STD_LOGIC_VECTOR (15 DOWNTO 0);
              signal fifo_reg_1_read_select :  STD_LOGIC;
              signal fifo_reg_1_write_select :  STD_LOGIC;
              signal fifo_reg_2 :  STD_LOGIC_VECTOR (15 DOWNTO 0);
              signal fifo_reg_2_read_select :  STD_LOGIC;
              signal fifo_reg_2_write_select :  STD_LOGIC;
              signal i_read_prime :  STD_LOGIC;
              signal internal_fifo_empty :  STD_LOGIC;
              signal internal_fifo_rd_data :  STD_LOGIC_VECTOR (15 DOWNTO 0);
              signal internal_fifo_read_data_bad :  STD_LOGIC;
              signal internal_i_read4 :  STD_LOGIC;
              signal next_read_pointer :  STD_LOGIC_VECTOR (2 DOWNTO 0);
              signal read_pointer :  STD_LOGIC_VECTOR (2 DOWNTO 0);
              signal unxxx146_in :  STD_LOGIC_VECTOR (2 DOWNTO 0);
              signal unxxx146_out :  STD_LOGIC_VECTOR (2 DOWNTO 0);
              signal unxxx154_in :  STD_LOGIC_VECTOR (2 DOWNTO 0);
              signal unxxx154_out :  STD_LOGIC_VECTOR (2 DOWNTO 0);
              signal write_pointer :  STD_LOGIC_VECTOR (2 DOWNTO 0);

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_fifo_empty <= '1';
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        if fifo_becoming_empty = '1' then 
          internal_fifo_empty <= '1';
        elsif (((fifo_write AND NOT fifo_read))) = '1' then 
          internal_fifo_empty <= '0';
        end if;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_i_read4 <= '1';
    elsif clk'event and clk = '1' then
      if ((NOT i_wait)) = '1' then 
        if fifo_becoming_empty = '1' then 
          internal_i_read4 <= '1';
        elsif (((((fifo_write AND NOT fifo_read)) OR (dont_forget_to_reset_i_read AND NOT internal_fifo_empty)))) = '1' then 
          internal_i_read4 <= '0';
        end if;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      dont_forget_to_reset_i_read <= '0';
    elsif clk'event and clk = '1' then
      if true then 
        if ((((dont_forget_to_reset_i_read AND NOT i_wait) OR (internal_fifo_empty AND dont_forget_to_reset_i_read)))) = '1' then 
          dont_forget_to_reset_i_read <= '0';
        elsif (((((fifo_write AND NOT fifo_read)) AND i_wait))) = '1' then 
          dont_forget_to_reset_i_read <= '1';
        end if;
      end if;
    end if;

  end process;

  fifo_inc <= fifo_write;
  fifo_dec <= fifo_read AND NOT internal_fifo_read_data_bad;
  next_read_pointer <= read_pointer(1 DOWNTO 0) & A_ToStdLogicVector(read_pointer(2));
  fifo_becoming_empty <= ((to_std_logic((next_read_pointer = write_pointer)) AND ((fifo_read AND NOT fifo_write)))) OR flush;
  i_read_prime <= internal_fifo_empty OR continue_read_cycle;
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      continue_read_cycle <= '0';
    elsif clk'event and clk = '1' then
      if true then 
        if ((NOT i_wait)) = '1' then 
          continue_read_cycle <= '0';
        elsif i_read_prime = '1' then 
          continue_read_cycle <= '1';
        end if;
      end if;
    end if;

  end process;

  internal_fifo_read_data_bad <= ((internal_fifo_empty AND NOT fifo_write)) OR flush;
  bad_news <= i_read_prime XOR internal_i_read4;
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      fifo_reg_0 <= "0000000000000000";
    elsif clk'event and clk = '1' then
      if (((fifo_reg_0_write_select AND fifo_write))) = '1' then 
        fifo_reg_0 <= fifo_wr_data;
      end if;
    end if;

  end process;

  fifo_reg_0_write_select <= write_pointer(0);
  fifo_reg_0_read_select <= read_pointer(0);
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      fifo_reg_1 <= "0000000000000000";
    elsif clk'event and clk = '1' then
      if (((fifo_reg_1_write_select AND fifo_write))) = '1' then 
        fifo_reg_1 <= fifo_wr_data;
      end if;
    end if;

  end process;

  fifo_reg_1_write_select <= write_pointer(1);
  fifo_reg_1_read_select <= read_pointer(1);
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      fifo_reg_2 <= "0000000000000000";
    elsif clk'event and clk = '1' then
      if (((fifo_reg_2_write_select AND fifo_write))) = '1' then 
        fifo_reg_2 <= fifo_wr_data;
      end if;
    end if;

  end process;

  fifo_reg_2_write_select <= write_pointer(2);
  fifo_reg_2_read_select <= read_pointer(2);
  internal_fifo_rd_data <= A_WE_StdLogicVector ((fifo_reg_0_read_select = '1'),fifo_reg_0,A_WE_StdLogicVector ((fifo_reg_1_read_select = '1'),fifo_reg_1,fifo_reg_2));
  fifo_rd_data <= A_WE_StdLogicVector ((internal_fifo_empty = '1'),fifo_wr_data,internal_fifo_rd_data);
  --rdaddress_calculator_reg, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      unxxx146_out <= "001";
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        unxxx146_out <= unxxx146_in;
      end if;
    end if;

  end process;

  unxxx146_in <= A_WE_StdLogicVector ((flush = '1'),"001",A_WE_StdLogicVector ((fifo_dec = '1'),(unxxx146_out(1 DOWNTO 0) & A_ToStdLogicVector(read_pointer(2))),unxxx146_out));
  read_pointer <= unxxx146_out;
  --wraddress_calculator_reg, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      unxxx154_out <= "001";
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        unxxx154_out <= unxxx154_in;
      end if;
    end if;

  end process;

  unxxx154_in <= A_WE_StdLogicVector ((flush = '1'),"001",A_WE_StdLogicVector ((fifo_inc = '1'),(unxxx154_out(1 DOWNTO 0) & A_ToStdLogicVector(write_pointer(2))),unxxx154_out));
  write_pointer <= unxxx154_out;
  --vhdl renameroo for output signals
  i_read <= internal_i_read4;
  --vhdl renameroo for output signals
  fifo_read_data_bad <= internal_fifo_read_data_bad;

end europa;


library altera_vhdl_support;