cpu.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

                 signal pipe_run : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal target_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);

              -- outputs:
                 signal i_flush : OUT STD_LOGIC;
                 signal p1_flush : OUT STD_LOGIC;
                 signal pc : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
              );

end entity cpu_address_request;


architecture europa of cpu_address_request is
              signal internal_p1_flush1 :  STD_LOGIC;
              signal internal_pc :  STD_LOGIC_VECTOR (19 DOWNTO 0);
              signal next_pc :  STD_LOGIC_VECTOR (19 DOWNTO 0);
              signal next_pc_plus_one :  STD_LOGIC_VECTOR (19 DOWNTO 0);
              signal nonsequential_pc :  STD_LOGIC;
              signal remember_to_flush :  STD_LOGIC;
              signal waiting_for_delay_slot :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_pc <= "00000000000000000000";
    elsif clk'event and clk = '1' then
      if ((((((((i_read OR internal_p1_flush1)) AND NOT i_wait)))))) = '1' then 
        internal_pc <= next_pc;
      end if;
    end if;

  end process;

  next_pc_plus_one <= internal_pc + "00000000000000000001";
  next_pc <= A_WE_StdLogicVector ((((((do_jump OR do_branch) OR remember_to_flush))) = '1'),target_address,next_pc_plus_one);
  nonsequential_pc <= ((do_branch OR do_jump)) AND pipe_run;
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      i_flush <= '0';
    elsif clk'event and clk = '1' then
      if ((NOT i_wait)) = '1' then 
        i_flush <= internal_p1_flush1;
      end if;
    end if;

  end process;

  internal_p1_flush1 <= ((nonsequential_pc AND NOT d1_instruction_fifo_read_data_bad)) OR ((remember_to_flush AND NOT waiting_for_delay_slot));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      remember_to_flush <= '0';
    elsif clk'event and clk = '1' then
      if true then 
        if (((internal_p1_flush1 AND NOT i_wait))) = '1' then 
          remember_to_flush <= '0';
        elsif ((((nonsequential_pc AND ((d1_instruction_fifo_read_data_bad OR i_wait)))))) = '1' then 
          remember_to_flush <= '1';
        end if;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      waiting_for_delay_slot <= '0';
    elsif clk'event and clk = '1' then
      if pipe_run = '1' then 
        if ((NOT instruction_fifo_read_data_bad)) = '1' then 
          waiting_for_delay_slot <= '0';
        elsif ((nonsequential_pc AND d1_instruction_fifo_read_data_bad)) = '1' then 
          waiting_for_delay_slot <= '1';
        end if;
      end if;
    end if;

  end process;

  --vhdl renameroo for output signals
  pc <= internal_pc;
  --vhdl renameroo for output signals
  p1_flush <= internal_p1_flush1;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity cpu_target_address is 
        port (
              -- inputs:
                 signal branch_base : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal do_branch : IN STD_LOGIC;
                 signal do_jump : IN STD_LOGIC;
                 signal jump_target_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
                 signal pipe_run : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal signed_branch_offset : IN STD_LOGIC_VECTOR (19 DOWNTO 0);

              -- outputs:
                 signal target_address : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
              );

end entity cpu_target_address;


architecture europa of cpu_target_address is
              signal branch_target_address :  STD_LOGIC_VECTOR (19 DOWNTO 0);
              signal current_target_address :  STD_LOGIC_VECTOR (19 DOWNTO 0);
              signal last_target_address :  STD_LOGIC_VECTOR (19 DOWNTO 0);

begin

  branch_target_address <= branch_base + signed_branch_offset;
  current_target_address <= A_WE_StdLogicVector ((do_jump = '1'),jump_target_address,branch_target_address);
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      last_target_address <= "00000000000000000000";
    elsif clk'event and clk = '1' then
      if ((((pipe_run AND (do_jump OR do_branch))))) = '1' then 
        last_target_address <= current_target_address;
      end if;
    end if;

  end process;

  target_address <= A_WE_StdLogicVector ((((do_jump OR do_branch)) = '1'),current_target_address,last_target_address);

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity cpu_instruction_fetch is 
        port (
              -- inputs:
                 signal branch_base : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
                 signal do_branch : IN STD_LOGIC;
                 signal do_jump : IN STD_LOGIC;
                 signal i_read : IN STD_LOGIC;
                 signal i_wait : IN STD_LOGIC;
                 signal instruction_fifo_read_data_bad : IN STD_LOGIC;
                 signal jump_target_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
                 signal pipe_run : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal signed_branch_offset : IN STD_LOGIC_VECTOR (19 DOWNTO 0);

              -- outputs:
                 signal i_address : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
                 signal i_flush : OUT STD_LOGIC;
                 signal p1_flush : OUT STD_LOGIC;
                 signal target_address : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
              );

attribute auto_dissolve : boolean ;
attribute auto_dissolve of cpu_instruction_fetch : entity is FALSE ;
end entity cpu_instruction_fetch;


architecture europa of cpu_instruction_fetch is
component cpu_address_request is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal d1_instruction_fifo_read_data_bad : IN STD_LOGIC;
                    signal do_branch : IN STD_LOGIC;
                    signal do_jump : IN STD_LOGIC;
                    signal i_read : IN STD_LOGIC;
                    signal i_wait : IN STD_LOGIC;
                    signal instruction_fifo_read_data_bad : IN STD_LOGIC;
                    signal pipe_run : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal target_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);

                 -- outputs:
                    signal i_flush : OUT STD_LOGIC;
                    signal p1_flush : OUT STD_LOGIC;
                    signal pc : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
                 );
end component cpu_address_request;

component cpu_target_address is 
           port (
                 -- inputs:
                    signal branch_base : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal do_branch : IN STD_LOGIC;
                    signal do_jump : IN STD_LOGIC;
                    signal jump_target_address : IN STD_LOGIC_VECTOR (19 DOWNTO 0);
                    signal pipe_run : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal signed_branch_offset : IN STD_LOGIC_VECTOR (19 DOWNTO 0);

                 -- outputs:
                    signal target_address : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
                 );
end component cpu_target_address;

              signal internal_i_flush3 :  STD_LOGIC;
              signal internal_p1_flush :  STD_LOGIC;
              signal internal_target_address :  STD_LOGIC_VECTOR (19 DOWNTO 0);
              signal pc :  STD_LOGIC_VECTOR (19 DOWNTO 0);

begin

  the_cpu_address_request : cpu_address_request
    port map(
      pc => pc,
      i_flush => internal_i_flush3,
      p1_flush => internal_p1_flush,
      do_jump => do_jump,
      i_read => i_read,
      i_wait => i_wait,
      target_address => internal_target_address,
      d1_instruction_fifo_read_data_bad => d1_instruction_fifo_read_data_bad,
      instruction_fifo_read_data_bad => instruction_fifo_read_data_bad,
      do_branch => do_branch,
      pipe_run => pipe_run,
      clk => clk,
      reset_n => reset_n