cnt.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

--      part of jop: used for mhz_counter
--	cnt.vhd
--
--	counter, interrrupt handling and watchdog bit
--
--	Author: Martin Schoeberl	[e-mail]
--
--		address map:
--
--			0	read clk counter, write irq ena
--			1	read 1 MHz counter, write timer val (us) + irq ack
--			2	write generates sw-int (for yield())
--			3	write wd port
--
--	todo:
--
--
--	2003-07-05	new IO standard
--	2003-08-15	us counter, irq added
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cnt is

port (
    -- needed for avalon interface
    	addr    : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
    	cs_n    : IN STD_LOGIC;
    --counter interface
	clk		: in std_logic;
	reset	: in std_logic;
	dout	: out std_logic_vector(31 downto 0)

);
end cnt ;

architecture rtl of cnt is

	signal clock_cnt		: std_logic_vector(31 downto 0);
	signal pre_scale		: std_logic_vector(7 downto 0);
	signal us_cnt			: std_logic_vector(31 downto 0);

--	constant div_val	: integer := clk_freq/1000000-1;
	constant div_val	: integer := 20000000/1000000-1;


begin


--
--	counter
--		pre_scale is 8 bit => fmax = 255 MHz
--
process(clk, reset) begin

	if (reset='1') then

		clock_cnt <= (others => '0');
		us_cnt <= (others => '0');
		pre_scale <= std_logic_vector(to_unsigned(div_val, pre_scale'length));

	elsif rising_edge(clk) then

		clock_cnt <= std_logic_vector(unsigned(clock_cnt) + 1);
		pre_scale <= std_logic_vector(unsigned(pre_scale) - 1);
		if pre_scale = "00000000" then
			pre_scale <= std_logic_vector(to_unsigned(div_val, pre_scale'length));
			us_cnt <= std_logic_vector(unsigned(us_cnt) + 1);
		end if;

	end if;
end process;

	dout <= us_cnt;
	
end rtl;