📄 nios_module.ptf
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{
priority = "1";
}
}
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "3";
}
PORT begintransfer
{
direction = "input";
type = "begintransfer";
width = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT dataavailable
{
direction = "output";
type = "dataavailable";
width = "1";
}
PORT irq
{
direction = "output";
type = "irq";
width = "1";
}
PORT read_n
{
direction = "input";
type = "read_n";
width = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "16";
}
PORT readyfordata
{
direction = "output";
type = "readyfordata";
width = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "16";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
View
{
Settings_Summary = "8-bit UART with 115200 baud, <br>
1 stop bits and N parity";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = " Bus Interface";
format = "Divider";
}
SIGNAL b
{
name = "chipselect";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "writedata";
radix = "hexadecimal";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL f
{
name = " Internals";
format = "Divider";
}
SIGNAL g
{
name = "tx_ready";
}
SIGNAL h
{
name = "tx_data";
radix = "ascii";
}
SIGNAL i
{
name = "rx_char_ready";
}
SIGNAL j
{
name = "rx_data";
radix = "ascii";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
baud = "115200";
data_bits = "8";
fixed_baud = "1";
parity = "N";
stop_bits = "1";
use_cts_rts = "0";
use_eop_register = "0";
sim_true_baud = "0";
sim_char_stream = "";
}
HDL_INFO
{
Simulation_HDL_Files = "__PROJECT_DIRECTORY__/nios_module_sim/uart_rx_stimulus_source_character_source_rom_module.vhd";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart.vhd";
}
PORT_WIRING
{
PORT rxd
{
direction = "input";
width = "1";
}
PORT txd
{
direction = "output";
width = "1";
}
}
}
MODULE timer
{
class = "altera_avalon_timer";
class_version = "2.0";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "0";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "0";
IRQ_Number = "17";
MASTERED_BY cpu/data_master
{
priority = "1";
}
Base_Address = "0x00000520";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
}
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "3";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT irq
{
direction = "output";
type = "irq";
width = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "16";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "16";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
View
{
Settings_Summary = "Timer with 1 msec timeout period.";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
always_run = "0";
fixed_period = "0";
snapshot = "1";
period = "1";
period_units = "msec";
reset_output = "0";
timeout_pulse_output = "0";
mult = "0.001";
}
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/timer.vhd";
}
PORT_WIRING
{
}
}
MODULE watchdog_pio
{
class = "altera_avalon_pio";
class_version = "2.0";
HDL_INFO
{
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/watchdog_pio.vhd";
}
PORT_WIRING
{
PORT out_port
{
direction = "output";
width = "1";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "2";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
IRQ_Number = "N/A";
Address_Width = "2";
Data_Width = "1";
Base_Address = "0x00000540";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu/data_master
{
priority = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
View
{
Settings_Summary = " 1-bit PIO using <br>
output pins";
MESSAGES
{
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
}
}
MODULE mhz_counter
{
class = "altera_avalon_user_defined_interface";
class_version = "2.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Date_Modified = "--unknown--";
View
{
MESSAGES
{
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Imported_Wait = "0";
Nios_Gen_Waits = "1";
Synthesize_Imported_HDL = "1";
Port_Type = "Avalon Slave";
HDL_Import = "1";
Timing_Units = "ns";
Address_Width = "32";
Module_List = "";
Component_Desc = "";
Component_Name = "";
Module_Name = "cnt";
Technology = "";
}
SLAVE avalonS
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Alignment = "native";
Address_Width = "2";
Data_Width = "32";
Has_IRQ = "0";
IRQ_Number = "N/A";
Base_Address = "0x00000580";
Has_Base_Address = "1";
Read_Wait_States = "0";
Write_Wait_States = "0";
Setup_Time = "0";
Hold_Time = "0";
Is_Memory_Device = "0";
Uses_Tri_State_Data_Bus = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
}
}
PORT_WIRING
{
PORT dout
{
direction = "output";
width = "32";
type = "readdata";
}
PORT clk
{
direction = "input";
width = "1";
type = "clk";
}
PORT reset
{
direction = "input";
width = "1";
type = "reset";
}
PORT addr
{
direction = "input";
width = "2";
type = "address";
}
PORT cs_n
{
direction = "input";
width = "1";
type = "chipselect_n";
}
}
}
MASTER avalonM
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Data_Width = "32";
Address_Width = "8";
Max_Address_Width = "32";
Is_Enabled = "0";
}
}
SLAVE ahbS
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "AHB";
Has_IRQ = "0";
IRQ_Number = "N/A";
Has_Base_Address = "1";
Address_Width = "10";
Data_Width = "32";
Base_Address = "--unknown--";
Address_Alignment = "native";
Read_Wait_States = "0";
Write_Wait_States = "0";
Is_Enabled = "0";
}
}
MASTER ahbM
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "AHB";
Address_Width = "32";
Max_Address_Width = "32";
Data_Width = "32";
Interrupts_Enabled = "1";
Irq_Scheme = "Individual_requests";
Is_Enabled = "0";
}
}
HDL_INFO
{
Imported_HDL_Files = "./cnt.vhd";
Synthesis_HDL_Files = "./cnt.vhd,__PROJECT_DIRECTORY__/mhz_counter.vhd";
}
}
}
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