📄 nios_module.ptf
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MESSAGES
{
}
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "6";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "32";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
PORT writebyteenable
{
direction = "input";
type = "writebyteenable";
width = "4";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "32";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Uses_Tri_State_Data_Bus = "0";
Address_Alignment = "dynamic";
Address_Width = "6";
Data_Width = "32";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "256";
Read_Latency = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
Base_Address = "0x00000400";
Is_Base_Locked = "0";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "chipselect";
conditional = "1";
}
SIGNAL b
{
name = "write";
conditional = "1";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "byteenable";
radix = "binary";
conditional = "1";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL f
{
name = "writedata";
radix = "hexadecimal";
conditional = "1";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Writeable = "1";
Size_Value = "256";
Size_Multiple = "1";
Contents = "blank";
Shrink_to_fit_contents = "0";
use_altsyncram = "0";
CONTENTS srec
{
Kind = "blank";
Build_Info = "";
Command_Info = "";
Textfile_Info = "";
String_Info = "";
}
}
PORT_WIRING
{
}
}
MODULE MUL_cpu
{
class = "altera_nios_multiply";
class_version = "2.0";
HDL_INFO
{
Simulation_HDL_Files = "__PROJECT_DIRECTORY__/nios_module_sim/MUL_cpu_black_box_module.vhd";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/MUL_cpu.vhd";
}
SLAVE s1
{
PORT_WIRING
{
PORT aclr
{
width = "1";
direction = "input";
type = "reset";
}
PORT clken
{
width = "1";
direction = "input";
type = "clk_en";
}
PORT clock
{
width = "1";
direction = "input";
type = "clk";
}
PORT dataa
{
width = "16";
direction = "input";
type = "dataa";
}
PORT datab
{
width = "16";
direction = "input";
type = "datab";
}
PORT result
{
width = "32";
direction = "output";
type = "result";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Alignment = "native";
Address_Width = "0";
Base_Address = "MUL5";
Is_Visible = "0";
MASTERED_BY cpu/custom_instruction_master
{
priority = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Is_Visible = "0";
Instantiate_In_System_Module = "1";
View
{
MESSAGES
{
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
ci_cycles = "3";
}
PORT_WIRING
{
}
}
MODULE boot_monitor_rom
{
class = "altera_avalon_onchip_memory";
class_version = "2.1";
HDL_INFO
{
Simulation_HDL_Files = "__PROJECT_DIRECTORY__/nios_module_sim/boot_monitor_rom_lane0_module.vhd";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/boot_monitor_rom.vhd";
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Required_Device_Family = "";
View
{
Settings_Summary = "1024-byte ROM, Contents: germs";
MESSAGES
{
}
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "8";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "32";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Uses_Tri_State_Data_Bus = "0";
Address_Alignment = "dynamic";
Address_Width = "8";
Data_Width = "32";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "1024";
Read_Latency = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
Base_Address = "0x00000000";
Is_Base_Locked = "1";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "chipselect";
conditional = "1";
}
SIGNAL b
{
name = "write";
conditional = "1";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "byteenable";
radix = "binary";
conditional = "1";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL f
{
name = "writedata";
radix = "hexadecimal";
conditional = "1";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Writeable = "0";
Size_Value = "1";
Size_Multiple = "1024";
Contents = "blank";
Shrink_to_fit_contents = "0";
use_altsyncram = "0";
CONTENTS srec
{
Kind = "germs";
Build_Info = "";
Command_Info = "";
Textfile_Info = "";
String_Info = "";
}
}
PORT_WIRING
{
}
}
MODULE tri_state_bridge
{
class = "altera_avalon_tri_state_bridge";
class_version = "2.0";
SLAVE avalon_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Bridges_To = "tristate_master";
Base_Address = "N/A";
Has_IRQ = "0";
IRQ = "N/A";
Register_Outgoing_Signals = "1";
Register_Incoming_Signals = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
}
}
MASTER tristate_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Bridges_To = "avalon_slave";
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Is_Bridge = "1";
View
{
MESSAGES
{
}
}
}
}
MODULE ext_ram
{
class = "altera_nios_dev_board_sram32";
class_version = "2.0";
HDL_INFO
{
}
WIZARD_SCRIPT_ARGUMENTS
{
sram_memory_size = "1024";
sram_memory_units = "1024";
sram_data_width = "32";
CONTENTS srec
{
Kind = "blank";
Build_Info = "";
Command_Info = "";
Textfile_Info = "";
String_Info = "";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "32";
is_shared = "1";
direction = "inout";
type = "data";
}
PORT address
{
width = "18";
is_shared = "1";
direction = "input";
type = "address";
}
PORT read_n
{
width = "1";
is_shared = "1";
direction = "input";
type = "read_n";
}
PORT write_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "write_n";
}
PORT be_n
{
width = "4";
is_shared = "1";
direction = "input";
type = "byteenable_n";
}
PORT select0_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
}
PORT select1_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Data_Width = "32";
Address_Width = "18";
Has_IRQ = "0";
IRQ_Number = "N/A";
Read_Wait_States = "0";
Write_Wait_States = "0";
Hold_Time = "half_clock";
Base_Address = "0x00100000";
Address_Span = "1048576";
MASTERED_BY tri_state_bridge/tristate_master
{
priority = "1";
}
Is_Base_Locked = "1";
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
Make_Memory_Model = "1";
View
{
MESSAGES
{
}
}
}
}
MODULE uart
{
class = "altera_avalon_uart";
class_version = "2.0";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "1";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "1";
IRQ_Number = "16";
Base_Address = "0x00000500";
Is_Base_Locked = "0";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
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