nios_module.ptf

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

SYSTEM nios_module
{
   WIZARD_SCRIPT_ARGUMENTS 
   {
      clock_freq = "20000000";
      generate_hdl = "1";
      generate_sdk = "1";
      do_build_sim = "0";
      skip_synth = "1";
      device_family = "CYCLONE";
      do_optimize = "0";
      leo_flatten = "0";
      leo_area = "1";
      hdl_language = "vhdl";
      view_master_columns = "0";
      view_master_priorities = "0";
      name_column_width = "155";
      desc_column_width = "155";
      bustype_column_width = "119";
      base_column_width = "79";
      end_column_width = "78";
      do_log_history = "0";
   }
   MODULE cpu
   {
      class = "altera_nios";
      class_version = "2.11";
      HDL_INFO 
      {
         Simulation_HDL_Files = "__PROJECT_DIRECTORY__/nios_module_sim/cpu_dpram_sim_model.vhd,__PROJECT_DIRECTORY__/nios_module_sim/cpu_dpram_module.vhd,__PROJECT_DIRECTORY__/nios_module_sim/cpu_instruction_decoder_rom_sim_model.vhd,__PROJECT_DIRECTORY__/nios_module_sim/cpu_instruction_decoder_rom.vhd";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu.vhd";
      }
      MASTER instruction_master
      {
         PORT_WIRING 
         {
            PORT i_address
            {
               direction = "output";
               type = "address";
               width = "21";
            }
            PORT i_datavalid
            {
               direction = "input";
               type = "readdatavalid";
               width = "1";
            }
            PORT i_flush
            {
               direction = "output";
               type = "flush";
               width = "1";
            }
            PORT i_read
            {
               direction = "output";
               type = "read";
               width = "1";
            }
            PORT i_readdata
            {
               direction = "input";
               type = "readdata";
               width = "16";
            }
            PORT i_wait
            {
               direction = "input";
               type = "waitrequest";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Data_Width = "16";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Max_Address_Width = "32";
         }
      }
      MASTER data_master
      {
         PORT_WIRING 
         {
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT d_address
            {
               direction = "output";
               type = "address";
               width = "21";
            }
            PORT d_byteenable
            {
               direction = "output";
               type = "byteenable";
               width = "4";
            }
            PORT d_read
            {
               direction = "output";
               type = "read";
               width = "1";
            }
            PORT d_readdata
            {
               direction = "input";
               type = "readdata";
               width = "32";
            }
            PORT d_wait
            {
               direction = "input";
               type = "waitrequest";
               width = "1";
            }
            PORT d_write
            {
               direction = "output";
               type = "write";
               width = "1";
            }
            PORT d_writedata
            {
               direction = "output";
               type = "writedata";
               width = "32";
            }
            PORT irq
            {
               direction = "input";
               type = "irq";
               width = "1";
            }
            PORT irqnumber
            {
               direction = "input";
               type = "irqnumber";
               width = "6";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "1";
            Bus_Type = "avalon";
            Data_Width = "32";
            Address_Width = "8";
            Is_Data_Master = "1";
            Max_Address_Width = "32";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         CPU_Architecture = "nios_32";
         mstep = "0";
         multiply = "1";
         rom_decoder = "1";
         wvalid_wr = "0";
         num_regs = "512";
         do_generate = "1";
         include_debug = "0";
         include_trace = "0";
         reset_slave = "boot_monitor_rom/s1";
         reset_offset = "0x00000000";
         vecbase_slave = "sys_ram/s1";
         vecbase_offset = "0x00000000";
         support_interrupts = "1";
         implement_forward_b1 = "1";
         support_rlc_rrc = "0";
         advanced = "1";
         CONSTANTS 
         {
            CONSTANT __nios_catch_irqs__
            {
               value = "0";
               comment = "Include panic handler for all irqs (needs uart)";
            }
            CONSTANT __nios_use_constructors__
            {
               value = "1";
               comment = "Call c++ static constructors";
            }
            CONSTANT __nios_use_cwpmgr__
            {
               value = "1";
               comment = "Handle register window underflows";
            }
            CONSTANT __nios_use_fast_mul__
            {
               value = "1";
               comment = "Faster but larger int multiply routine";
            }
            CONSTANT __nios_use_small_printf__
            {
               value = "1";
               comment = "Smaller non-ANSI printf, with no floating point";
            }
            CONSTANT __nios_use_multiply__
            {
               value = "1";
               comment = "Use MUL instruction for 16x16";
            }
            CONSTANT __nios_use_mstep__
            {
               value = "0";
               comment = "Use MSTEP instruction for 16x16";
            }
         }
         mainmem_slave = "ext_ram/s1";
         datamem_slave = "ext_ram/s1";
         maincomm_slave = "uart/s1";
         debugcomm_slave = "uart/s1";
         germs_monitor_id = "cyclone32";
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_CPU = "1";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         View 
         {
            Settings_Summary = "nios_32 with 512 registers.";
            MESSAGES 
            {
            }
         }
      }
      SIMULATION 
      {
         Fix_Me_Up = "sim_generate1";
         DISPLAY 
         {
            SIGNAL a
            {
               name = "__FIX_ME_UP__/instruction_display/instruction_opcode";
               format = "Literal";
            }
            SIGNAL b
            {
               name = "  instruction master";
               format = "Divider";
            }
            SIGNAL c
            {
               name = "i_address";
               radix = "hexadecimal";
            }
            SIGNAL d
            {
               name = "i_readdata";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "__FIX_ME_UP__/i_readdata_display/i_readdata_opcode";
               format = "Literal";
            }
            SIGNAL f
            {
               name = "i_wait";
            }
            SIGNAL g
            {
               name = "i_read";
            }
            SIGNAL h
            {
               name = "i_datavalid";
            }
            SIGNAL i
            {
               name = "i_flush";
            }
            SIGNAL j
            {
               name = "  data master";
               format = "Divider";
            }
            SIGNAL k
            {
               name = "d_write";
            }
            SIGNAL l
            {
               name = "d_address";
               radix = "hexadecimal";
            }
            SIGNAL m
            {
               name = "d_read";
            }
            SIGNAL n
            {
               name = "d_readdata";
               radix = "hexadecimal";
            }
            SIGNAL o
            {
               name = "d_wait";
            }
            SIGNAL p
            {
               name = "d_byteenable";
               radix = "binary";
            }
            SIGNAL q
            {
               name = "d_writedata";
               radix = "hexadecimal";
            }
            SIGNAL r
            {
               name = "  interrupts";
               format = "Divider";
            }
            SIGNAL s
            {
               name = "irq";
            }
            SIGNAL t
            {
               name = "irqnumber";
               radix = "unsigned";
            }
         }
         MODELSIM 
         {
            SETUP_COMMANDS 
            {
               i_readdata_vfn = "virtual function { (cpu_nios_opcode_type) __MODULE_PATH__/__FIX_ME_UP__/i_readdata_display/i_readdata_opcode_bits } i_readdata_opcode";
               i_readdata_vsig = "virtual signal { __MODULE_PATH__/__FIX_ME_UP__/i_readdata_display/opcode[6:0] } i_readdata_opcode_bits";
               instruction_vfn = "virtual function { (cpu_nios_opcode_type) __MODULE_PATH__/__FIX_ME_UP__/instruction_display/instruction_opcode_bits } instruction_opcode";
               instruction_vsig = "virtual signal { __MODULE_PATH__/__FIX_ME_UP__/instruction_display/opcode[6:0] } instruction_opcode_bits";
            }
            TYPES 
            {
               type1 = "virtual type { ADD EXT8s ADDI EXT16s SUB ST8s SUBI ST16s CMP CMPI SAVE LSL TRAP LSLI JMPC LSR CALLC LSRI ASR NOT ASRI NEG MOV ABS MOVI SEXT8 AND SEXT16 ANDN RLC OR RRC XOR BGEN SWAP EXT8d SKP0 SKP1 LD ST STS8s STS16s RESTORE TRET ST8d EXT16d ST16d MOVHI FILL8 USR0 FILL16 MSTEP BR MUL BSR SKPRz LDC SKPS PFX WRCTL STP RDCTL LDP SKPRnz STS JMP LDS CALL } cpu_nios_opcode_type";
            }
         }
      }
      MASTER custom_instruction_master
      {
         PORT_WIRING 
         {
            PORT custom_instruction_clk_en
            {
               direction = "output";
               type = "clk_en";
               width = "1";
            }
            PORT custom_instruction_dataa
            {
               direction = "output";
               type = "dataa";
               width = "32";
            }
            PORT custom_instruction_datab
            {
               direction = "output";
               type = "datab";
               width = "32";
            }
            PORT custom_instruction_prefix
            {
               direction = "output";
               type = "prefix";
               width = "11";
            }
            PORT custom_instruction_reset
            {
               direction = "output";
               type = "reset";
               width = "1";
            }
            PORT custom_instruction_result
            {
               direction = "input";
               type = "result";
               width = "32";
            }
            PORT custom_instruction_start
            {
               direction = "output";
               type = "start";
               width = "6";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "nios_custom_instruction";
            Data_Width = "32";
            Address_Width = "3";
            Base_Address = "N/A";
            Is_Visible = "0";
            Is_Custom_Instruction = "0";
         }
      }
      PORT_WIRING 
      {
      }
   }
   System_Wizard_Version = "2.7";
   MODULE USR0_cpu
   {
      class = "altera_nios_custom_instr_divide";
      class_version = "2.0";
      HDL_INFO 
      {
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/USR0_cpu.vhd";
         Simulation_HDL_Files = "";
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT dataa
            {
               width = "32";
               direction = "input";
               type = "dataa";
            }
            PORT datab
            {
               width = "32";
               direction = "input";
               type = "datab";
            }
            PORT result
            {
               width = "32";
               direction = "output";
               type = "result";
            }
            PORT clk
            {
               width = "1";
               direction = "input";
               type = "clk";
            }
            PORT clk_en
            {
               width = "1";
               direction = "input";
               type = "clk_en";
            }
            PORT reset
            {
               width = "1";
               direction = "input";
               type = "reset";
            }
            PORT start
            {
               width = "1";
               direction = "input";
               type = "start";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "nios_custom_instruction";
            Data_Width = "32";
            Address_Width = "0";
            Base_Address = "USR0";
            Is_Custom_Instruction = "1";
            Is_Visible = "0";
            MASTERED_BY cpu/custom_instruction_master
            {
               priority = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Is_Visible = "0";
         Instantiate_In_System_Module = "1";
         Is_Custom_Instruction = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Module_Name = "divide_instruction_unit";
         ci_macro_name = "divi";
         ci_operands = "2";
         ci_cycles = "35";
         Has_Prefix = "0";
         Synthesize_Imported_HDL = "1";
         ci_instr_format = "RR";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE sys_ram
   {
      class = "altera_avalon_onchip_memory";
      class_version = "2.1";
      HDL_INFO 
      {
         Simulation_HDL_Files = "__PROJECT_DIRECTORY__/nios_module_sim/sys_ram_lane3_module.vhd,__PROJECT_DIRECTORY__/nios_module_sim/sys_ram_lane2_module.vhd,__PROJECT_DIRECTORY__/nios_module_sim/sys_ram_lane1_module.vhd,__PROJECT_DIRECTORY__/nios_module_sim/sys_ram_lane0_module.vhd";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_ram.vhd";
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Required_Device_Family = "";
         View 
         {
            Settings_Summary = "256-byte RAM, Contents: blank";