excalibur.h

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

			"PFX 3 \n		\
			WRCTL %1 \n		\
			PFX 4 \n		\
			WRCTL %0;"		\
			: /* no outputs */	\
			:"r"(val),"r"(offset)	\
		);

//Set breakpoint 0
#define nm_debug_set_bp0(ap,am,dp,dm,cd) nm_debug_set_reg(ap,np_debug_address_pattern_0);\
				       nm_debug_set_reg(am,np_debug_address_mask_0);\
				       nm_debug_set_reg(dp,np_debug_data_pattern_0);\
				       nm_debug_set_reg(dm,np_debug_data_mask_0);\
				       nm_debug_set_reg(cd,np_debug_code_0);

//Set breakpoint 1
#define nm_debug_set_bp1(ap,am,dp,dm,cd) nm_debug_set_reg(ap,np_debug_address_pattern_1);\
				       nm_debug_set_reg(am,np_debug_address_mask_1);\
				       nm_debug_set_reg(dp,np_debug_data_pattern_1);\
				       nm_debug_set_reg(dm,np_debug_data_mask_1);\
				       nm_debug_set_reg(cd,np_debug_code_1);

//Set extended trace mode
#define nm_debug_set_extended_trace nm_debug_set_reg(1,np_debug_trace_mode);

//Set memory interrupt point
#define nm_debug_set_wrap_point(size) nm_debug_set_reg((size>>2),np_debug_mem_int_enable);

// UART Registers
typedef volatile struct
	{
	int np_uartrxdata;      // Read-only, 8-bit
	int np_uarttxdata;      // Write-only, 8-bit
	int np_uartstatus;      // Read-only, 8-bit
	int np_uartcontrol;     // Read/Write, 9-bit
	int np_uartdivisor;     // Read/Write, 16-bit, optional
	int np_uartendofpacket; // Read/Write, end-of-packet character
	} np_uart;

// UART Status Register Bits
enum
	{
	np_uartstatus_eop_bit  = 12,
	np_uartstatus_cts_bit  = 11,
	np_uartstatus_dcts_bit = 10,
	np_uartstatus_e_bit    = 8,
	np_uartstatus_rrdy_bit = 7,
	np_uartstatus_trdy_bit = 6,
	np_uartstatus_tmt_bit  = 5,
	np_uartstatus_toe_bit  = 4,
	np_uartstatus_roe_bit  = 3,
	np_uartstatus_brk_bit  = 2,
	np_uartstatus_fe_bit   = 1,
	np_uartstatus_pe_bit   = 0,

	np_uartstatus_eop_mask  = (1<<12),
	np_uartstatus_cts_mask  = (1<<11),
	np_uartstatus_dcts_mask = (1<<10),
	np_uartstatus_e_mask    = (1<<8),
	np_uartstatus_rrdy_mask = (1<<7),
	np_uartstatus_trdy_mask = (1<<6),
	np_uartstatus_tmt_mask  = (1<<5),
	np_uartstatus_toe_mask  = (1<<4),
	np_uartstatus_roe_mask  = (1<<3),
	np_uartstatus_brk_mask  = (1<<2),
	np_uartstatus_fe_mask   = (1<<1),
	np_uartstatus_pe_mask   = (1<<0)
	};

// UART Control Register Bits
enum
	{
	np_uartcontrol_ieop_bit  = 12,
	np_uartcontrol_rts_bit   = 11,
	np_uartcontrol_idcts_bit = 10,
	np_uartcontrol_tbrk_bit  = 9,
	np_uartcontrol_ie_bit    = 8,
	np_uartcontrol_irrdy_bit = 7,
	np_uartcontrol_itrdy_bit = 6,
	np_uartcontrol_itmt_bit  = 5,
	np_uartcontrol_itoe_bit  = 4,
	np_uartcontrol_iroe_bit  = 3,
	np_uartcontrol_ibrk_bit  = 2,
	np_uartcontrol_ife_bit   = 1,
	np_uartcontrol_ipe_bit   = 0,

	np_uartcontrol_ieop_mask  = (1<<12),
	np_uartcontrol_rts_mask   = (1<<11),
	np_uartcontrol_idcts_mask = (1<<10),
	np_uartcontrol_tbrk_mask  = (1<<9),
	np_uartcontrol_ie_mask    = (1<<8),
	np_uartcontrol_irrdy_mask = (1<<7),
	np_uartcontrol_itrdy_mask = (1<<6),
	np_uartcontrol_itmt_mask  = (1<<5),
	np_uartcontrol_itoe_mask  = (1<<4),
	np_uartcontrol_iroe_mask  = (1<<3),
	np_uartcontrol_ibrk_mask  = (1<<2),
	np_uartcontrol_ife_mask   = (1<<1),
	np_uartcontrol_ipe_mask   = (1<<0)
	};

// UART Routines
int nr_uart_rxchar(np_uart *uartBase);        // 0 for default UART
void nr_uart_txcr(void);
void nr_uart_txchar(int c,np_uart *uartBase); // 0 for default UART
void nr_uart_txhex(int x);                     // 16 or 32 bits
void nr_uart_txhex16(short x);
void nr_uart_txhex32(long x);
void nr_uart_txstring(char *s);


// ----------------------------------------------
// Timer Peripheral

// Timer Registers
typedef volatile struct
	{
	int np_timerstatus;  // read only, 2 bits (any write to clear TO)
	int np_timercontrol; // write/readable, 4 bits
	int np_timerperiodl; // write/readable, 16 bits
	int np_timerperiodh; // write/readable, 16 bits
	int np_timersnapl;   // read only, 16 bits
	int np_timersnaph;   // read only, 16 bits
	} np_timer;

// Timer Register Bits
enum
	{
	np_timerstatus_run_bit    = 1, // timer is running
	np_timerstatus_to_bit     = 0, // timer has timed out

	np_timercontrol_stop_bit  = 3, // stop the timer
	np_timercontrol_start_bit = 2, // start the timer
	np_timercontrol_cont_bit  = 1, // continous mode
	np_timercontrol_ito_bit   = 0, // enable time out interrupt

	np_timerstatus_run_mask    = (1<<1), // timer is running
	np_timerstatus_to_mask     = (1<<0), // timer has timed out

	np_timercontrol_stop_mask  = (1<<3), // stop the timer
	np_timercontrol_start_mask = (1<<2), // start the timer
	np_timercontrol_cont_mask  = (1<<1), // continous mode
	np_timercontrol_ito_mask   = (1<<0)  // enable time out interrupt
	};

// Timer Routines
int nr_timer_milliseconds(void);	// Starts on first call, hogs timer1.

// PIO Peripheral

// PIO Registers
typedef volatile struct
	{
	int np_piodata;          // read/write, up to 32 bits
	int np_piodirection;     // write/readable, up to 32 bits, 1->output bit
	int np_piointerruptmask; // write/readable, up to 32 bits, 1->enable interrupt
	int np_pioedgecapture;   // read, up to 32 bits, cleared by any write
	} np_pio;

// PIO Routines
void nr_pio_showhex(int value); // shows low byte on pio named na_seven_seg_pio


// ----------------------------------------------
// mhz_counter

typedef volatile struct 
  {
  int np_cnt_val;
  } np_mhz_counter;





// ===========================================================
// Parameters for Each Peripheral, Excerpted From The PTF File



// ------------------
// Parameters for altera_nios_custom_instr_divide named USR0_cpu

// Module_Name             = divide_instruction_unit
// ci_macro_name           = divi
// ci_operands             = 2
// ci_cycles               = 35
// Has_Prefix              = 0
// Synthesize_Imported_HDL = 1
// ci_instr_format         = RR



// ------------------
// Parameters for altera_nios_multiply named MUL_cpu

// ci_cycles = 3



// ------------------
// Parameters for altera_avalon_onchip_memory named boot_monitor_rom

// Writeable              = 0
// Size_Value             = 1
// Size_Multiple          = 1024
// Contents               = blank
// Shrink_to_fit_contents = 0
// use_altsyncram         = 0
// CONTENTS               = srec



// ------------------
// Parameters for altera_nios named cpu

// CPU_Architecture     = nios_32
// mstep                = 0
// multiply             = 1
// rom_decoder          = 1
// wvalid_wr            = 0
// num_regs             = 512
// do_generate          = 1
// include_debug        = 0
// include_trace        = 0
// reset_slave          = boot_monitor_rom/s1
// reset_offset         = 0x00000000
// vecbase_slave        = sys_ram/s1
// vecbase_offset       = 0x00000000
// support_interrupts   = 1
// implement_forward_b1 = 1
// support_rlc_rrc      = 0
// advanced             = 1
// CONSTANTS            =
// mainmem_slave        = ext_ram/s1
// datamem_slave        = ext_ram/s1
// maincomm_slave       = uart/s1
// debugcomm_slave      = uart/s1
// germs_monitor_id     = cyclone32



// ------------------
// Parameters for altera_avalon_onchip_memory named sys_ram

// Writeable              = 1
// Size_Value             = 256
// Size_Multiple          = 1
// Contents               = blank
// Shrink_to_fit_contents = 0
// use_altsyncram         = 0
// CONTENTS               = srec



// ------------------
// Parameters for altera_avalon_uart named uart

// baud             = 115200
// data_bits        = 8
// fixed_baud       = 1
// parity           = N
// stop_bits        = 1
// use_cts_rts      = 0
// use_eop_register = 0
// sim_true_baud    = 0
// sim_char_stream  =



// ------------------
// Parameters for altera_avalon_timer named timer

// always_run           = 0
// fixed_period         = 0
// snapshot             = 1
// period               = 1
// period_units         = msec
// reset_output         = 0
// timeout_pulse_output = 0
// mult                 = 0.001



// ------------------
// Parameters for altera_avalon_pio named watchdog_pio

// has_tri   = 0
// has_out   = 1
// has_in    = 0
// capture   = 0
// edge_type = NONE
// irq_type  = NONE



// ------------------
// Parameters for altera_avalon_user_defined_interface named mhz_counter

// Imported_Wait           = 0
// Nios_Gen_Waits          = 1
// Synthesize_Imported_HDL = 1
// Port_Type               = Avalon Slave
// HDL_Import              = 1
// Timing_Units            = ns
// Address_Width           = 32
// Module_List             =
// Component_Desc          =
// Component_Name          =
// Module_Name             = cnt
// Technology              =



// ------------------
// Parameters for altera_nios_dev_board_sram32 named ext_ram

// sram_memory_size  = 1024
// sram_memory_units = 1024
// sram_data_width   = 32
// CONTENTS          = srec



#ifdef __cplusplus
}
#endif

#endif //_excalibur_

// end of file