excalibur.h

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

/*
 * File: excalibur.h
 *
 * This file is a machine generated address map
 * for a CPU named cpu.
 * H:/qdesigns/old/cyclone32/nios_module.ptf
 * Generated: 2004.01.23 11:35:46
 */

#ifndef _excalibur_
#define _excalibur_

#ifdef __cplusplus
extern "C" {
#endif

// The Memory Map

#define na_MUL_cpu               ((void *)          0x00000000) // altera_nios_multiply
#define na_MUL_cpu_base                             0x00000000
#define na_MUL_cpu_end           ((void *)          0x00000004)
#define na_MUL_cpu_size                             0x00000004
#define na_boot_monitor_rom      ((void *)          0x00000000) // altera_avalon_onchip_memory
#define na_boot_monitor_rom_base                    0x00000000
#define na_boot_monitor_rom_end  ((void *)          0x00000400)
#define na_boot_monitor_rom_size                    0x00000400
#define na_cpu                   ((void *)          0x00000000) // altera_nios
#define na_cpu_base                                 0x00000000
#define na_sys_ram               ((void *)          0x00000400) // altera_avalon_onchip_memory
#define na_sys_ram_base                             0x00000400
#define na_sys_ram_end           ((void *)          0x00000500)
#define na_sys_ram_size                             0x00000100
#define na_uart                  ((np_uart *)       0x00000500) // altera_avalon_uart
#define na_uart_base                                0x00000500
#define na_uart_irq                                 16
#define na_timer                 ((np_timer *)      0x00000520) // altera_avalon_timer
#define na_timer_base                               0x00000520
#define na_timer_irq                                17
#define na_watchdog_pio          ((np_pio *)        0x00000540) // altera_avalon_pio
#define na_watchdog_pio_base                        0x00000540
#define na_mhz_counter           ((np_mhz_counter *) 0x00000580) // altera_avalon_user_defined_interface
#define na_mhz_counter_base                         0x00000580
#define na_ext_ram               ((void *)          0x00100000) // altera_nios_dev_board_sram32
#define na_ext_ram_base                             0x00100000
#define na_ext_ram_end           ((void *)          0x00200000)
#define na_ext_ram_size                             0x00100000
 
#define na_null                           0
#define nasys_pio_count                   1
#define nasys_pio_0                       na_watchdog_pio
#define nasys_timer_count                 1
#define nasys_timer_0                     na_timer
#define nasys_timer_0_irq                 17
#define nasys_uart_count                  1
#define nasys_uart_0                      na_uart
#define nasys_uart_0_irq                  16
#define nasys_usersocket_count            1
#define nasys_usersocket_0                na_mhz_counter
#define nasys_vector_table      ((int *)  0x00000400)
#define nasys_vector_table_size           0x00000100
#define nasys_vector_table_end  ((int *)  0x00000500)
#define nasys_reset_address     ((void *) 0x00000000)
#define nasys_clock_freq                  20000000
#define nasys_clock_freq_1000             20000
#define nasys_debug_core                  0
#define nasys_printf_uart                 na_uart
#define nasys_printf_uart_irq             na_uart_irq
#define nm_printf_txchar                  nr_uart_txchar
#define nm_printf_rxchar                  nr_uart_rxchar
#define nasys_debug_uart                  na_uart
#define nasys_debug_uart_irq              na_uart_irq
#define nasys_program_mem       ((void *) 0x00100000)
#define nasys_program_mem_size            0x00100000
#define nasys_program_mem_end   ((void *) 0x00200000)
#define nasys_data_mem          ((void *) 0x00100000)
#define nasys_data_mem_size               0x00100000
#define nasys_data_mem_end      ((void *) 0x00200000)
#define nasys_stack_top         ((void *) 0x00200000)
 
#define __nios_catch_irqs__        0 // Include panic handler for all irqs (needs uart)
#define __nios_use_constructors__  1 // Call c++ static constructors
#define __nios_use_cwpmgr__        1 // Handle register window underflows
#define __nios_use_fast_mul__      1 // Faster but larger int multiply routine
#define __nios_use_small_printf__  1 // Smaller non-ANSI printf, with no floating point
#define __nios_use_multiply__      1 // Use MUL instruction for 16x16
#define __nios_use_mstep__         0 // Use MSTEP instruction for 16x16



#define nm_system_name_string "nios_module"
#define nm_cpu_name_string "cpu"
#define nm_monitor_string "cyclone32"
#define nm_cpu_architecture nios_32
#define nm_cpu_architecture_string "nios_32"
#define nios_32 1

// Structures and Routines For Each Peripheral

#define nm_divi(_x,_y) ({\
	int __x = (_x), __y = (_y);\
	asm volatile("usr0 %0,%2 ; does divi" \
	: "=r" (__x) \
	: "0" (__x), "r" (__y));\
	__x;\
	})

// Nios CPU Routines
void nr_installcwpmanager(void);	// called automatically at by nr_setup.s
void nr_delay(int milliseconds);	// approximate timing based on clock speed
void nr_zerorange(char *rangeStart,int rangeByteCount);
void nr_jumptoreset(void);

// Nios ISR Manager Routines
typedef void (*nios_isrhandlerproc)(int context);
typedef void (*nios_isrhandlerproc2)(int context,int irq_number,int interruptee_pc);
void nr_installuserisr(int trapNumber,nios_isrhandlerproc handlerProc,int context);
void nr_installuserisr2(int trapNumber,nios_isrhandlerproc2 handlerProc,int context);

// Nios GDB Stub Functions
void nios_gdb_install(int active);
#define nios_gdb_breakpoint() asm("TRAP 5")

// Default UART routines
void nr_txchar(int c);
void nr_txstring(char *s);
int nr_rxchar(void);

// Debug UART routines
void nr_debug_txchar(int c);
void nr_debug_txstring(char *s);
int nr_debug_rxchar(void);

// Nios Private Printf Routines
int nr_printf(const char *fmt,...);
int nr_sprintf(char *sOut,const char *fmt,...);

#if __nios_use_small_printf__
	#define printf nr_printf
	#define sprintf nr_sprintf
#endif

#ifdef na_enet
void nios_gdb_install_ethernet(int active);
int nr_debug_plugs_idle ();
#endif

#if __nios_debug__
	#define NIOS_GDB_SETUP 		\
		nios_gdb_install(1);	\
		nios_gdb_breakpoint();
#else
	#define NIOS_GDB_SETUP
#endif

// Nios setjmp/longjmp support
// (This will collide with <setjmp.h>
// if you include it! These are the
// nios-correct versions, however.)

typedef int jmp_buf[2];

int nr_setjmp(jmp_buf env);
int nr_longjmp(jmp_buf env,int value);

#define setjmp(a) nr_setjmp((a))
#define longjmp(a,b) nr_longjmp((a),(b))


// debug Core Declarations

#define nasys_debug_core_irq                8

// debug registers offsets from base
enum
{
    np_debug_interrupt =		0,		//read-only,  4 bits, reading stops trace
    np_debug_n_samples_lsb,			//read-only, 16 bits
    np_debug_n_samples_msb,			//read-only, 16 bits
    np_debug_data_valid,				//read-only, 1 bit, 
    						//true when trace registers contain valid sample
    np_debug_trace_address,			//read-only, 16 or 32 bits
    np_debug_trace_data,				//read-only, 16 or 32 bits
    np_debug_trace_code,				//read-only, 16 or 32 bits
    np_debug_write_status,			//read-only, 1 bit, 
    						//true when read to readback tracedata
    np_debug_start,				//write-only, write any value to start
    np_debug_stop,				//write-only, write any value to stop
    np_debug_read_sample,				//write-only, write any value to read
    np_debug_trace_mode,				//write-only, 1 bit
    np_debug_mem_int_enable,			//write-only, 16 or 32 bits ?????
    np_debug_ext_brk_enable,			//write-only, 1 bit
    np_debug_sw_reset,				//write-only, reset sampels and trace memory

    np_debug_address_pattern_0 =	16,		//write-only, 16 or 32 bits
    np_debug_address_mask_0,			//write-only, 16 or 32 bits
    np_debug_data_pattern_0,			//write-only, 16 or 32 bits
    np_debug_data_mask_0,				//write-only, 16 or 32 bits
    np_debug_code_0,				//write-only, 16 or 32 bits

    np_debug_address_pattern_1 =	24,		//write-only, 16 or 32 bits
    np_debug_address_mask_1,			//write-only, 16 or 32 bits
    np_debug_data_pattern_1,			//write-only, 16 or 32 bits
    np_debug_data_mask_1,				//write-only, 16 or 32 bits
    np_debug_code_1,				//write-only, 16 or 32 bits
};

// debug Register Bits/Codes
enum 
{ 
    /************************************************/
    // debug_interrupt register
    // bit numbers
    np_debug_interrupt_code_dbp0_bit = 0,
    np_debug_interrupt_code_dbp1_bit = 1,
    np_debug_interrupt_code_ibp0_bit = 2,
    np_debug_interrupt_code_ibp1_bit = 3,
    np_debug_interrupt_code_mem_bit = 4,

    // bit masks
    np_debug_interrupt_code_ext_mask = (0), 
    np_debug_interrupt_code_dbp0_mask = (1<<0),
    np_debug_interrupt_code_dbp1_mask = (1<<1),
    np_debug_interrupt_code_ibp0_mask = (1<<2),
    np_debug_interrupt_code_ibp1_mask = (1<<3),
    np_debug_interrupt_code_mem_mask = (1<<4),

    /************************************************/
    // debug_trace_code register
    // bit numbers
    np_debug_trace_code_skp_bit = 1,
    np_debug_trace_code_fifo_full_bit = 2,
    np_debug_trace_code_bus_bit = 3,
    np_debug_trace_code_rw_bit = 4,
    np_debug_trace_code_intr_bit = 5,
    
    // bit masks
    np_debug_trace_code_skp_mask = (1<<0),
    np_debug_trace_code_fifo_full_mask = (1<<1),
    np_debug_trace_code_data_trans_mask = (1<<2), //instr trans if 0
    np_debug_trace_code_write_mask = (1<<3),	//read if 0
    np_debug_trace_code_intr_mask = (1<<4),
#ifdef __nios32__
    np_debug_trace_code_skp_cnt_mask = (63<<2),
#else
    np_debug_trace_code_skp_cnt_mask = (31<<2),
#endif

    // useful constants
    np_debug_trace_code_op_mask = (np_debug_trace_code_data_trans_mask|np_debug_trace_code_write_mask),
    np_debug_trace_code_read = np_debug_trace_code_data_trans_mask,
    np_debug_trace_code_write = (np_debug_trace_code_data_trans_mask|np_debug_trace_code_write_mask),
    np_debug_trace_code_fetch = 0,

    /************************************************/
    // debug_code_* registers
    // bit numbers
    np_debug_break_code_read_bit = 0,
    np_debug_break_code_write_bit = 1,
    np_debug_break_code_fetch_bit = 2,

    // bit masks
    np_debug_break_code_read_mask = (1<<0),
    np_debug_break_code_write_mask = (1<<1),
    np_debug_break_code_fetch_mask = (1<<2),

    /************************************************/
    // debug_write_status register
    // bit numbers
    np_debug_write_status_writing_bit = 0,
    np_debug_write_status_nios32_bit = 1,
    np_debug_write_status_trace_bit = 2,

    // bit masks
    np_debug_write_status_writing_mask = (1<<0),
    np_debug_write_status_nios32_mask = (1<<1),
    np_debug_write_status_trace_mask = (1<<2)
};

// debug Routine


//Get the number of trace samples 
unsigned long nr_debug_num_samples (void);	

//Stop debug core - this must be a function so that a branch is the last
//                  thing in the fifo.  Otherwise a skip or a read/write
//                  might be logged without the ability to sync it up
void nr_debug_stop (void);

//Read a trace sample
void nr_debug_get_sample (unsigned int *trace_addr, 
			unsigned int *trace_data, 
			unsigned char *trace_code);

//must have a uart for these functions
#ifdef nasys_uart_count
#if (nasys_uart_count > 0)

  //print cause of break
  void nr_debug_show_break (void *uart);
                                  // 0 for default printf uart

  //dump the trace memory
  void nr_debug_dump_trace (void *uart);
                             // 0 for defualt printf uart

  //ISR for debug interrupts
  //Show cause of break, dump trace, and halt
  void nr_debug_isr_halt (int context);		
                            // 0 for default printf uart otherwise uart base address

  //Show cause of break, dump trace, and continue
  void nr_debug_isr_continue (int context);		
                                // 0 for default printf uart otherwise uart base address

#endif
#endif

// debug macros
//Read a debug register
#define nm_debug_get_reg(ret, offset) 		\
		asm volatile (			\
			"PFX 3 \n		\
			WRCTL %1 \n		\
			PFX 4 \n		\
			RDCTL %0;"		\
			:"=r" (ret)		\
			:"r"(offset)		\
		);

//Write a debug register
#define nm_debug_set_reg(val,offset) 		\
		asm volatile (			\