📄 excalibur.s
字号:
;; File: excalibur.s;; This file is a machine generated address map; for a CPU named cpu using toolchain "gnu".; H:/qdesigns/old/cyclone32/nios_module.ptf; Generated: 2004.01.23 11:35:47;.ifndef _excalibur_.equ _excalibur_,1 ; minor macro to .equate and .global .macro GEQU sym,val .global \sym .equ \sym,\val .endm; The Memory Map GEQU na_MUL_cpu , 0x00000000 ; altera_nios_multiply GEQU na_MUL_cpu_end , 0x00000004 GEQU na_boot_monitor_rom , 0x00000000 ; altera_avalon_onchip_memory GEQU na_boot_monitor_rom_end , 0x00000400 GEQU na_cpu , 0x00000000 ; altera_nios GEQU na_sys_ram , 0x00000400 ; altera_avalon_onchip_memory GEQU na_sys_ram_end , 0x00000500 GEQU na_uart , 0x00000500 ; altera_avalon_uart GEQU na_uart_irq , 16 GEQU na_timer , 0x00000520 ; altera_avalon_timer GEQU na_timer_irq , 17 GEQU na_watchdog_pio , 0x00000540 ; altera_avalon_pio GEQU na_mhz_counter , 0x00000580 ; altera_avalon_user_defined_interface GEQU na_ext_ram , 0x00100000 ; altera_nios_dev_board_sram32 GEQU na_ext_ram_end , 0x00200000 GEQU na_null , 0 GEQU nasys_pio_count , 1 GEQU nasys_pio_0 , na_watchdog_pio GEQU nasys_timer_count , 1 GEQU nasys_timer_0 , na_timer GEQU nasys_timer_0_irq , 17 GEQU nasys_uart_count , 1 GEQU nasys_uart_0 , na_uart GEQU nasys_uart_0_irq , 16 GEQU nasys_usersocket_count , 1 GEQU nasys_usersocket_0 , na_mhz_counter GEQU nasys_vector_table , 0x00000400 GEQU nasys_vector_table_size , 0x00000100 GEQU nasys_vector_table_end , 0x00000500 GEQU nasys_reset_address , 0x00000000 GEQU nasys_clock_freq , 20000000 GEQU nasys_clock_freq_1000 , 20000 GEQU nasys_debug_core , 0 GEQU nasys_printf_uart , na_uart GEQU nasys_printf_uart_irq , na_uart_irq GEQU nasys_debug_uart , na_uart GEQU nasys_debug_uart_irq , na_uart_irq GEQU nasys_program_mem , 0x00100000 GEQU nasys_program_mem_size , 0x00100000 GEQU nasys_program_mem_end , 0x00200000 GEQU nasys_data_mem , 0x00100000 GEQU nasys_data_mem_size , 0x00100000 GEQU nasys_data_mem_end , 0x00200000 GEQU nasys_stack_top , 0x00200000 .equ __nios_catch_irqs__ , 0 ; Include panic handler for all irqs (needs uart) .equ __nios_use_constructors__ , 1 ; Call c++ static constructors .equ __nios_use_cwpmgr__ , 1 ; Handle register window underflows .equ __nios_use_fast_mul__ , 1 ; Faster but larger int multiply routine .equ __nios_use_small_printf__ , 1 ; Smaller non-ANSI printf, with no floating point .equ __nios_use_multiply__ , 1 ; Use MUL instruction for 16x16 .equ __nios_use_mstep__ , 0 ; Use MSTEP instruction for 16x16 .macro nm_system_name_string .asciz "nios_module" .endm .macro nm_cpu_name_string .asciz "cpu" .endm .macro nm_monitor_string .asciz "cyclone32" .endm .equ nios_32,1 .macro nm_cpu_architecture .asciz "nios_32" .endm; Structures and Routines For Each Peripheral .macro nm_divi,_x,_y usr0 \_x,\_y .endm
.include "nios_macros.s"
.ifdef __nios32__
.equ nios_wordsize,4
.else
.equ nios_wordsize,2
.endif
GEQU nasys_debug_core_irq, 8
;;; debug registers offsets from base
GEQU np_debug_interrupt, 0 ;read-only, 4 bits, reading stops trace
GEQU np_debug_n_samples_lsb, 1 ;read-only, 16 bits
GEQU np_debug_n_samples_msb, 2 ;read-only, 16 bits
GEQU np_debug_data_valid, 3 ;read-only, 1 bit,
;true when trace registers contain valid sample
GEQU np_debug_trace_address, 4 ;read-only, 16 or 32 bits
GEQU np_debug_trace_data, 5 ;read-only, 16 or 32 bits
GEQU np_debug_trace_code, 6 ;read-only, 16 or 32 bits
GEQU np_debug_write_status, 7 ;read-only, 1 bit,
;true when read to readback tracedata
GEQU np_debug_start, 8 ;write-only, write any value to start
GEQU np_debug_stop, 9 ;write-only, write any value to stop
GEQU np_debug_read_sample, 10 ;write-only, write any value to read
GEQU np_debug_trace_mode, 11 ;write-only, 1 bit
GEQU np_debug_mem_int_enable, 12 ;write-only, 16 or 32 bits ?????
GEQU np_debug_ext_brk_enable, 13 ;write-only, 1 bit
GEQU np_debug_sw_reset, 14 ;write-only, reset sampels and trace memory
GEQU np_debug_address_pattern_0,16 ;write-only, 16 or 32 bits
GEQU np_debug_address_mask_0, 17 ;write-only, 16 or 32 bits
GEQU np_debug_data_pattern_0, 18 ;write-only, 16 or 32 bits
GEQU np_debug_data_mask_0, 19 ;write-only, 16 or 32 bits
GEQU np_debug_code_0, 20 ;write-only, 16 or 32 bits
GEQU np_debug_address_pattern_1,24 ;write-only, 16 or 32 bits
GEQU np_debug_address_mask_1, 25 ;write-only, 16 or 32 bits
GEQU np_debug_data_pattern_1, 26 ;write-only, 16 or 32 bits
GEQU np_debug_data_mask_1, 27 ;write-only, 16 or 32 bits
GEQU np_debug_code_1, 28 ;write-only, 16 or 32 bits
;;; debug Register Bits/Codes
;;; ************************************************
;;; debug_interrupt register
;;; bit numbers
GEQU np_debug_interrupt_code_dbp0_bit, 0
GEQU np_debug_interrupt_code_dbp1_bit, 1
GEQU np_debug_interrupt_code_ibp0_bit, 2
GEQU np_debug_interrupt_code_ibp1_bit, 3
GEQU np_debug_interrupt_code_mem_bit, 4
;;; bit masks
GEQU np_debug_interrupt_code_ext_mask, (0)
GEQU np_debug_interrupt_code_dbp0_mask, (1<<0)
GEQU np_debug_interrupt_code_dbp1_mask, (1<<1)
GEQU np_debug_interrupt_code_ibp0_mask, (1<<2)
GEQU np_debug_interrupt_code_ibp1_mask, (1<<3)
GEQU np_debug_interrupt_code_mem_mask, (1<<4)
;;; ************************************************
;;; debug_trace_code register
;;; bit numbers
GEQU np_debug_trace_code_skp_bit, 1
GEQU np_debug_trace_code_fifo_full_bit, 2
GEQU np_debug_trace_code_bus_bit, 3
GEQU np_debug_trace_code_rw_bit, 4
GEQU np_debug_trace_code_intr_bit, 5
;;; bit masks
GEQU np_debug_trace_code_skp_mask, (1<<0)
GEQU np_debug_trace_code_fifo_full_mask, (1<<1)
GEQU np_debug_trace_code_data_trans_mask,(1<<2) ;instr trans if 0
GEQU np_debug_trace_code_write_mask, (1<<3) ;read if 0
GEQU np_debug_trace_code_intr_mask, (1<<4)
.ifdef __nios32__
GEQU np_debug_trace_code_skp_cnt_mask, (63<<2)
.else
GEQU np_debug_trace_code_skp_cnt_mask, (31<<2)
.endif
;;; useful constants
GEQU np_debug_trace_code_op_mask, (np_debug_trace_code_data_trans_mask|np_debug_trace_code_write_mask)
GEQU np_debug_trace_code_read, np_debug_trace_code_data_trans_mask
GEQU np_debug_trace_code_write, (np_debug_trace_code_data_trans_mask|np_debug_trace_code_write_mask)
GEQU np_debug_trace_code_fetch, 0
;;; ************************************************
;;; debug_code_* registers
;;; bit numbers
GEQU np_debug_break_code_read_bit, 0
GEQU np_debug_break_code_write_bit, 1
GEQU np_debug_break_code_fetch_bit, 2
;;; bit masks
GEQU np_debug_break_code_read_mask, (1<<0)
GEQU np_debug_break_code_write_mask, (1<<1)
GEQU np_debug_break_code_fetch_mask, (1<<2)
;;; ************************************************
;;; debug_write_status register
;;; bit numbers
GEQU np_debug_write_status_writing_bit, 0
GEQU np_debug_write_status_nios32_bit, 1
GEQU np_debug_write_status_trace_bit, 2
;;; bit masks
GEQU np_debug_write_status_writing_mask, (1<<0)
GEQU np_debug_write_status_nios32_mask, (1<<1)
GEQU np_debug_write_status_trace_mask, (1<<2)
; ----------------------------------------------
; UART Peripheral
;
;
; UART Registers
;
.equ np_uartrxdata, 0 ; Read-only, 8-bit
.equ np_uarttxdata, 1 ; Write-only, 8-bit
.equ np_uartstatus, 2 ; Read-only, 8-bit
.equ np_uartcontrol, 3 ; Read/Write, 9-bit
.equ np_uartdivisor, 4 ; Read/Write, 16-bit, optional
.equ np_uartendofpacket, 5 ; Read/Write, end-of-packet character
;
; UART Status Register
;
.equ np_uartstatus_eop_mask, (1<<12)
.equ np_uartstatus_cts_mask, (1<<11)
.equ np_uartstatus_dcts_mask, (1<<10)
.equ np_uartstatus_e_mask, (1<<8)
.equ np_uartstatus_rrdy_mask, (1<<7)
.equ np_uartstatus_trdy_mask, (1<<6)
.equ np_uartstatus_tmt_mask, (1<<5)
.equ np_uartstatus_toe_mask, (1<<4)
.equ np_uartstatus_roe_mask, (1<<3)
.equ np_uartstatus_brk_mask, (1<<2)
.equ np_uartstatus_fe_mask, (1<<1)
.equ np_uartstatus_pe_mask, (1<<0)
.equ np_uartstatus_eop_bit, 12
.equ np_uartstatus_cts_bit, 11
.equ np_uartstatus_dcts_bit, 10
.equ np_uartstatus_e_bit, 8
.equ np_uartstatus_rrdy_bit, 7
.equ np_uartstatus_trdy_bit, 6
.equ np_uartstatus_tmt_bit, 5
.equ np_uartstatus_toe_bit, 4
.equ np_uartstatus_roe_bit, 3
.equ np_uartstatus_brk_bit, 2
.equ np_uartstatus_fe_bit, 1
.equ np_uartstatus_pe_bit, 0
;
; UART Control Register
;
.equ np_uartcontrol_eop_mask, (1<<10)
.equ np_uartcontrol_tbrk_mask, (1<<9)
.equ np_uartcontrol_ie_mask, (1<<8)
.equ np_uartcontrol_irrdy_mask, (1<<7)
.equ np_uartcontrol_itrdy_mask, (1<<6)
.equ np_uartcontrol_itmt_mask, (1<<5)
.equ np_uartcontrol_itoe_mask, (1<<4)
.equ np_uartcontrol_iroe_mask, (1<<3)
.equ np_uartcontrol_ibrk_mask, (1<<2)
.equ np_uartcontrol_ife_mask, (1<<1)
.equ np_uartcontrol_ipe_mask, (1<<0)
.equ np_uartcontrol_eop_bit, 10
.equ np_uartcontrol_tbrk_bit, 9
.equ np_uartcontrol_ie_bit, 8
.equ np_uartcontrol_irrdy_bit, 7
.equ np_uartcontrol_itrdy_bit, 6
.equ np_uartcontrol_itmt_bit, 5
.equ np_uartcontrol_itoe_bit, 4
.equ np_uartcontrol_iroe_bit, 3
.equ np_uartcontrol_ibrk_bit, 2
.equ np_uartcontrol_ife_bit, 1
.equ np_uartcontrol_ipe_bit, 0
; ----------------------------------------------
; Timer Peripheral
;
;
; Timer Register Offsets
;
.equ np_timerstatus, 0 ; read only, 2 bits (any write to clear to)
.equ np_timercontrol, 1 ; write/readable, 4 bits
.equ np_timerperiodl, 2 ; write/readable, 16 bits
.equ np_timerperiodh, 3 ; write/readable, 16 bits
.equ np_timersnapl, 4 ; read only, 16 bits
.equ np_timersnaph, 5 ; read only, 16 bits
;
; Timer Register Bits
;
.equ np_timerstatus_run_bit, 1 ; timer is running
.equ np_timerstatus_to_bit, 0 ; timer has timed out
.equ np_timercontrol_stop_bit, 3 ; stop the timer
.equ np_timercontrol_start_bit, 2 ; start the timer
.equ np_timercontrol_cont_bit, 1 ; continous mode
.equ np_timercontrol_ito_bit, 0 ; enable time out interrupt
.equ np_timerstatus_run_mask, (1<<1) ; timer is running
.equ np_timerstatus_tO_mask, (1<<0) ; timer has timed out
.equ np_timercontrol_stop_mask, (1<<3) ; stop the timer
.equ np_timercontrol_start_mask, (1<<2) ; start the timer
.equ np_timercontrol_cont_mask, (1<<1) ; continous mode
.equ np_timercontrol_ito_mask, (1<<0) ; enable time out interrupt
; ----------------------------------------------
; PIO Peripheral
;
;
; PIO Registers
;
.equ np_piodata, 0 ; read/write, up to 32 bits
.equ np_piodirection, 1 ; write/readable, up to 32 bits, 1->output bit
.equ np_piointerruptmask, 2 ; write/readable, up to 32 bits, 1->enable interrupt
.equ np_pioedgecapture, 3 ; read, up to 32 bits, cleared by any write.
.endif ; _excalibur_; end of file⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -