uart.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

              signal any_error :  STD_LOGIC;
              signal control_reg :  STD_LOGIC_VECTOR (9 DOWNTO 0);
              signal control_wr_strobe :  STD_LOGIC;
              signal cts_status_bit :  STD_LOGIC;
              signal d1_rx_char_ready :  STD_LOGIC;
              signal d1_tx_ready :  STD_LOGIC;
              signal dcts_status_bit :  STD_LOGIC;
              signal delayed_unxxx155 :  STD_LOGIC;
              signal divisor_constant :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal do_write_char :  STD_LOGIC;
              signal eop_status_bit :  STD_LOGIC;
              signal ie_any_error :  STD_LOGIC;
              signal ie_break_detect :  STD_LOGIC;
              signal ie_framing_error :  STD_LOGIC;
              signal ie_parity_error :  STD_LOGIC;
              signal ie_rx_char_ready :  STD_LOGIC;
              signal ie_rx_overrun :  STD_LOGIC;
              signal ie_tx_overrun :  STD_LOGIC;
              signal ie_tx_ready :  STD_LOGIC;
              signal ie_tx_shift_empty :  STD_LOGIC;
              signal internal_tx_data :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal internal_tx_wr_strobe :  STD_LOGIC;
              signal qualified_irq :  STD_LOGIC;
              signal selected_read_data :  STD_LOGIC_VECTOR (15 DOWNTO 0);
              signal status_reg :  STD_LOGIC_VECTOR (12 DOWNTO 0);
  constant simulating2 : boolean :=
-- exemplar translate_off
--###{
--    true OR
--###}
-- exemplar translate_on
    false;

begin

--exemplar translate_off
sim_generate1:if simulating2 generate
    begin
      --delayed_unxxx155, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        delayed_unxxx155 <= '0';
      elsif clk'event and clk = '1' then
        if clk_en = '1' then 
          delayed_unxxx155 <= tx_ready;
        end if;
      end if;

    end process;

    do_write_char <= tx_ready AND NOT delayed_unxxx155;

      process (clk)
    VARIABLE write_line : line;
    begin
      if clk'event and clk = '1' then
        if do_write_char = '1' then 
          write(write_line, character'val(CONV_INTEGER(internal_tx_data)));
          write(write_line, string'(""));
          write(output, write_line.all);
          deallocate (write_line);
        end if;
      end if;

    end process;


      divisor_constant <= "00000100";

  end generate sim_generate1;
--exemplar translate_on
  synthesis_generate1:if NOT simulating2 generate
    begin
      divisor_constant <= "10101110";

  end generate synthesis_generate1;
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      readdata <= "0000000000000000";
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        readdata <= selected_read_data;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      irq <= '0';
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        irq <= qualified_irq;
      end if;
    end if;

  end process;

  rx_rd_strobe <= to_std_logic((((((chipselect AND NOT read_n) = '1') AND (address = "000")))));
  internal_tx_wr_strobe <= to_std_logic((((((chipselect AND NOT write_n) = '1') AND (address = "001")))));
  status_wr_strobe <= to_std_logic((((((chipselect AND NOT write_n) = '1') AND (address = "010")))));
  control_wr_strobe <= to_std_logic((((((chipselect AND NOT write_n) = '1') AND (address = "011")))));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_tx_data <= "00000000";
    elsif clk'event and clk = '1' then
      if internal_tx_wr_strobe = '1' then 
        internal_tx_data <= writedata(7 DOWNTO 0);
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      control_reg <= "0000000000";
    elsif clk'event and clk = '1' then
      if control_wr_strobe = '1' then 
        control_reg <= writedata(9 DOWNTO 0);
      end if;
    end if;

  end process;

  baud_divisor <= divisor_constant;
  cts_status_bit <= '0';
  dcts_status_bit <= '0';
  (do_force_break, ie_any_error, ie_rx_char_ready, ie_tx_ready, ie_tx_shift_empty, ie_tx_overrun, ie_rx_overrun, ie_break_detect, ie_framing_error, ie_parity_error) <= control_reg;
  any_error <= tx_overrun OR rx_overrun OR parity_error OR framing_error OR break_detect;
  status_reg <= Std_Logic_Vector'(A_ToStdLogicVector(eop_status_bit) & A_ToStdLogicVector(cts_status_bit) & A_ToStdLogicVector(dcts_status_bit) & A_ToStdLogicVector('0') & A_ToStdLogicVector(any_error) & A_ToStdLogicVector(rx_char_ready) & A_ToStdLogicVector(tx_ready) & A_ToStdLogicVector(tx_shift_empty) & A_ToStdLogicVector(tx_overrun) & A_ToStdLogicVector(rx_overrun) & A_ToStdLogicVector(break_detect) & A_ToStdLogicVector(framing_error) & A_ToStdLogicVector(parity_error));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_rx_char_ready <= '0';
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        d1_rx_char_ready <= rx_char_ready;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_tx_ready <= '0';
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        d1_tx_ready <= tx_ready;
      end if;
    end if;

  end process;

  dataavailable <= d1_rx_char_ready;
  readyfordata <= d1_tx_ready;
  eop_status_bit <= '0';
  selected_read_data <= ((((Std_Logic_Vector'(A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000"))) & A_ToStdLogicVector(to_std_logic((address = "000")))) AND ("00000000" & rx_data))) OR ((Std_Logic_Vector'(A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001"))) & A_ToStdLogicVector(to_std_logic((address = "001")))) AND ("00000000" & internal_tx_data)))) OR ((Std_Logic_Vector'(A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010"))) & A_ToStdLogicVector(to_std_logic((address = "010")))) AND ("000" & status_reg)))) OR ((Std_Logic_Vector'(A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011"))) & A_ToStdLogicVector(to_std_logic((address = "011")))) AND ("000000" & control_reg)));
  qualified_irq <= (ie_any_error AND any_error) OR (ie_tx_shift_empty AND tx_shift_empty) OR (ie_tx_overrun AND tx_overrun) OR (ie_rx_overrun AND rx_overrun) OR (ie_break_detect AND break_detect) OR (ie_framing_error AND framing_error) OR (ie_parity_error AND parity_error) OR (ie_rx_char_ready AND rx_char_ready) OR (ie_tx_ready AND tx_ready);
  --vhdl renameroo for output signals
  tx_wr_strobe <= internal_tx_wr_strobe;
  --vhdl renameroo for output signals
  tx_data <= internal_tx_data;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity uart is 
        port (
              -- inputs:
                 signal address : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal begintransfer : IN STD_LOGIC;
                 signal chipselect : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal read_n : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal rxd : IN STD_LOGIC;
                 signal write_n : IN STD_LOGIC;
                 signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

              -- outputs:
                 signal dataavailable : OUT STD_LOGIC;
                 signal irq : OUT STD_LOGIC;
                 signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal readyfordata : OUT STD_LOGIC;
                 signal txd : OUT STD_LOGIC
              );

end entity uart;


architecture europa of uart is
component uart_tx is 
           port (
                 -- inputs:
                    signal baud_divisor : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal begintransfer : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal clk_en : IN STD_LOGIC;
                    signal do_force_break : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal status_wr_strobe : IN STD_LOGIC;
                    signal tx_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal tx_wr_strobe : IN STD_LOGIC;

                 -- outputs:
                    signal tx_overrun : OUT STD_LOGIC;
                    signal tx_ready : OUT STD_LOGIC;
                    signal tx_shift_empty : OUT STD_LOGIC;
                    signal txd : OUT STD_LOGIC
                 );
end component uart_tx;

component uart_rx is 
           port (
                 -- inputs:
                    signal baud_divisor : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal begintransfer : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal clk_en : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal rx_rd_strobe : IN STD_LOGIC;
                    signal rxd : IN STD_LOGIC;
                    signal status_wr_strobe : IN STD_LOGIC;

                 -- outputs:
                    signal break_detect : OUT STD_LOGIC;
                    signal framing_error : OUT STD_LOGIC;
                    signal parity_error : OUT STD_LOGIC;
                    signal rx_char_ready : OUT STD_LOGIC;
                    signal rx_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal rx_overrun : OUT STD_LOGIC
                 );
end component uart_rx;

component uart_regs is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                    signal break_detect : IN STD_LOGIC;
                    signal chipselect : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal clk_en : IN STD_LOGIC;
                    signal framing_error : IN STD_LOGIC;
                    signal parity_error : IN STD_LOGIC;
                    signal read_n : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal rx_char_ready : IN STD_LOGIC;
                    signal rx_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal rx_overrun : IN STD_LOGIC;
                    signal tx_overrun : IN STD_LOGIC;
                    signal tx_ready : IN STD_LOGIC;
                    signal tx_shift_empty : IN STD_LOGIC;
                    signal write_n : IN STD_LOGIC;
                    signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

                 -- outputs:
                    signal baud_divisor : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal dataavailable : OUT STD_LOGIC;
                    signal do_force_break : OUT STD_LOGIC;
                    signal irq : OUT STD_LOGIC;
                    signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal readyfordata : OUT STD_LOGIC;
                    signal rx_rd_strobe : OUT STD_LOGIC;
                    signal status_wr_strobe : OUT STD_LOGIC;
                    signal tx_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal tx_wr_strobe : OUT STD_LOGIC
                 );
end component uart_regs;

              signal baud_divisor :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal break_detect :  STD_LOGIC;
              signal clk_en :  STD_LOGIC;
              signal do_force_break :  STD_LOGIC;
              signal framing_error :  STD_LOGIC;
              signal internal_dataavailable :  STD_LOGIC;
              signal internal_irq :  STD_LOGIC;
              signal internal_readdata :  STD_LOGIC_VECTOR (15 DOWNTO 0);
              signal internal_readyfordata :  STD_LOGIC;
              signal internal_txd :  STD_LOGIC;
              signal parity_error :  STD_LOGIC;
              signal rx_char_ready :  STD_LOGIC;
              signal rx_data :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal rx_overrun :  STD_LOGIC;
              signal rx_rd_strobe :  STD_LOGIC;
              signal status_wr_strobe :  STD_LOGIC;
              signal tx_data :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal tx_overrun :  STD_LOGIC;
              signal tx_ready :  STD_LOGIC;
              signal tx_shift_empty :  STD_LOGIC;
              signal tx_wr_strobe :  STD_LOGIC;

begin

  clk_en <= '1';
  the_uart_tx : uart_tx
    port map(
      tx_shift_empty => tx_shift_empty,
      txd => internal_txd,
      tx_overrun => tx_overrun,
      tx_ready => tx_ready,
      clk_en => clk_en,
      status_wr_strobe => status_wr_strobe,
      tx_wr_strobe => tx_wr_strobe,
      baud_divisor => baud_divisor,
      clk => clk,
      do_force_break => do_force_break,
      tx_data => tx_data,
      begintransfer => begintransfer,
      reset_n => reset_n
    );


  the_uart_rx : uart_rx
    port map(
      framing_error => framing_error,
      parity_error => parity_error,
      rx_char_ready => rx_char_ready,
      break_detect => break_detect,
      rx_overrun => rx_overrun,
      rx_data => rx_data,
      clk_en => clk_en,
      status_wr_strobe => status_wr_strobe,
      rxd => rxd,
      baud_divisor => baud_divisor,
      clk => clk,
      begintransfer => begintransfer,
      rx_rd_strobe => rx_rd_strobe,
      reset_n => reset_n
    );


  the_uart_regs : uart_regs
    port map(
      readdata => internal_readdata,
      status_wr_strobe => status_wr_strobe,
      tx_wr_strobe => tx_wr_strobe,
      baud_divisor => baud_divisor,
      readyfordata => internal_readyfordata,
      dataavailable => internal_dataavailable,
      do_force_break => do_force_break,
      irq => internal_irq,
      tx_data => tx_data,
      rx_rd_strobe => rx_rd_strobe,
      framing_error => framing_error,
      rx_char_ready => rx_char_ready,
      clk_en => clk_en,
      rx_overrun => rx_overrun,
      chipselect => chipselect,
      read_n => read_n,
      clk => clk,
      tx_overrun => tx_overrun,
      tx_shift_empty => tx_shift_empty,
      writedata => writedata,
      parity_error => parity_error,
      break_detect => break_detect,
      address => address,
      rx_data => rx_data,
      write_n => write_n,
      reset_n => reset_n,
      tx_ready => tx_ready
    );


  --vhdl renameroo for output signals
  readdata <= internal_readdata;
  --vhdl renameroo for output signals
  readyfordata <= internal_readyfordata;
  --vhdl renameroo for output signals
  dataavailable <= internal_dataavailable;
  --vhdl renameroo for output signals
  txd <= internal_txd;
  --vhdl renameroo for output signals
  irq <= internal_irq;

end europa;