📄 uart.vhd
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d4_aboriginal_start_pulse <= '0';
d5_aboriginal_start_pulse <= '0';
d6_aboriginal_start_pulse <= '0';
d7_aboriginal_start_pulse <= '0';
d8_aboriginal_start_pulse <= '0';
d9_aboriginal_start_pulse <= '0';
startup_pulse <= '0';
elsif clk'event and clk = '1' then
if clk_en = '1' then
d1_aboriginal_start_pulse <= aboriginal_start_pulse;
d2_aboriginal_start_pulse <= d1_aboriginal_start_pulse;
d3_aboriginal_start_pulse <= d2_aboriginal_start_pulse;
d4_aboriginal_start_pulse <= d3_aboriginal_start_pulse;
d5_aboriginal_start_pulse <= d4_aboriginal_start_pulse;
d6_aboriginal_start_pulse <= d5_aboriginal_start_pulse;
d7_aboriginal_start_pulse <= d6_aboriginal_start_pulse;
d8_aboriginal_start_pulse <= d7_aboriginal_start_pulse;
d9_aboriginal_start_pulse <= d8_aboriginal_start_pulse;
startup_pulse <= d9_aboriginal_start_pulse;
end if;
end if;
end process;
do_send_stim_data <= (pickup_pulse OR startup_pulse) AND NOT address_is_last;
end generate sim_generate;
--exemplar translate_on
synthesis_generate:if NOT simulating1 generate
begin
internal_source_rxd <= rxd;
end generate synthesis_generate;
--vhdl renameroo for output signals
source_rxd <= internal_source_rxd;
end europa;
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity uart_rx is
port (
-- inputs:
signal baud_divisor : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal begintransfer : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal clk_en : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal rx_rd_strobe : IN STD_LOGIC;
signal rxd : IN STD_LOGIC;
signal status_wr_strobe : IN STD_LOGIC;
-- outputs:
signal break_detect : OUT STD_LOGIC;
signal framing_error : OUT STD_LOGIC;
signal parity_error : OUT STD_LOGIC;
signal rx_char_ready : OUT STD_LOGIC;
signal rx_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_overrun : OUT STD_LOGIC
);
end entity uart_rx;
architecture europa of uart_rx is
component uart_rx_stimulus_source is
port (
-- inputs:
signal baud_divisor : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal clk : IN STD_LOGIC;
signal clk_en : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal rx_char_ready : IN STD_LOGIC;
signal rxd : IN STD_LOGIC;
-- outputs:
signal source_rxd : OUT STD_LOGIC
);
end component uart_rx_stimulus_source;
signal baud_clk_en : STD_LOGIC;
signal baud_load_value : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal baud_rate_counter : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal baud_rate_counter_is_zero : STD_LOGIC;
signal d1_source_rxd : STD_LOGIC;
signal delayed_unxxx120 : STD_LOGIC;
signal delayed_unxxx89 : STD_LOGIC;
signal delayed_unxxx92 : STD_LOGIC;
signal do_start_rx : STD_LOGIC;
signal got_new_char : STD_LOGIC;
signal half_bit_cell_divisor : STD_LOGIC_VECTOR (6 DOWNTO 0);
signal internal_rx_char_ready : STD_LOGIC;
signal is_break : STD_LOGIC;
signal is_framing_error : STD_LOGIC;
signal raw_data_in : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_in_process : STD_LOGIC;
signal rx_rd_strobe_onset : STD_LOGIC;
signal rxd_edge : STD_LOGIC;
signal rxd_falling : STD_LOGIC;
signal rxd_shift_reg : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal sample_enable : STD_LOGIC;
signal shift_reg_start_bit_n : STD_LOGIC;
signal source_rxd : STD_LOGIC;
signal stop_bit : STD_LOGIC;
signal sync_rxd : STD_LOGIC;
signal unused_start_bit : STD_LOGIC;
signal unxxx108_in : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal unxxx108_out : STD_LOGIC_VECTOR (9 DOWNTO 0);
begin
the_uart_rx_stimulus_source : uart_rx_stimulus_source
port map(
source_rxd => source_rxd,
rx_char_ready => internal_rx_char_ready,
clk_en => clk_en,
rxd => rxd,
baud_divisor => baud_divisor,
clk => clk,
reset_n => reset_n
);
process (clk, reset_n)
begin
if reset_n = '0' then
d1_source_rxd <= '0';
sync_rxd <= '0';
elsif clk'event and clk = '1' then
if clk_en = '1' then
d1_source_rxd <= source_rxd;
sync_rxd <= d1_source_rxd;
end if;
end if;
end process;
--delayed_unxxx89, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
delayed_unxxx89 <= '0';
elsif clk'event and clk = '1' then
if clk_en = '1' then
delayed_unxxx89 <= sync_rxd;
end if;
end if;
end process;
rxd_falling <= NOT sync_rxd AND delayed_unxxx89;
--delayed_unxxx92, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
delayed_unxxx92 <= '0';
elsif clk'event and clk = '1' then
if clk_en = '1' then
delayed_unxxx92 <= sync_rxd;
end if;
end if;
end process;
rxd_edge <= sync_rxd XOR delayed_unxxx92;
rx_rd_strobe_onset <= rx_rd_strobe AND begintransfer;
half_bit_cell_divisor <= baud_divisor(7 DOWNTO 1);
baud_load_value <= A_WE_StdLogicVector ((rxd_edge = '1'),("0" & half_bit_cell_divisor),baud_divisor);
process (clk, reset_n)
begin
if reset_n = '0' then
baud_rate_counter <= "00000000";
elsif clk'event and clk = '1' then
if clk_en = '1' then
if ((baud_rate_counter_is_zero OR rxd_edge)) = '1' then
baud_rate_counter <= baud_load_value;
else
baud_rate_counter <= baud_rate_counter - "00000001";
end if;
end if;
end if;
end process;
baud_rate_counter_is_zero <= to_std_logic((baud_rate_counter = "00000000"));
process (clk, reset_n)
begin
if reset_n = '0' then
baud_clk_en <= '0';
elsif clk'event and clk = '1' then
if clk_en = '1' then
if rxd_edge = '1' then
baud_clk_en <= '0';
else
baud_clk_en <= baud_rate_counter_is_zero;
end if;
end if;
end if;
end process;
sample_enable <= baud_clk_en AND rx_in_process;
process (clk, reset_n)
begin
if reset_n = '0' then
do_start_rx <= '0';
elsif clk'event and clk = '1' then
if clk_en = '1' then
if ((NOT rx_in_process AND rxd_falling)) = '1' then
do_start_rx <= '1';
else
do_start_rx <= '0';
end if;
end if;
end if;
end process;
rx_in_process <= shift_reg_start_bit_n;
(stop_bit, raw_data_in(7), raw_data_in(6), raw_data_in(5), raw_data_in(4), raw_data_in(3), raw_data_in(2), raw_data_in(1), raw_data_in(0), unused_start_bit) <= rxd_shift_reg;
is_break <= NOT (or_reduce(rxd_shift_reg));
is_framing_error <= NOT stop_bit AND NOT is_break;
--delayed_unxxx120, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
delayed_unxxx120 <= '0';
elsif clk'event and clk = '1' then
if clk_en = '1' then
delayed_unxxx120 <= rx_in_process;
end if;
end if;
end process;
got_new_char <= NOT rx_in_process AND delayed_unxxx120;
process (clk, reset_n)
begin
if reset_n = '0' then
rx_data <= "00000000";
elsif clk'event and clk = '1' then
if got_new_char = '1' then
rx_data <= raw_data_in;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
framing_error <= '0';
elsif clk'event and clk = '1' then
if clk_en = '1' then
if status_wr_strobe = '1' then
framing_error <= '0';
elsif ((got_new_char AND is_framing_error)) = '1' then
framing_error <= '1';
end if;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
break_detect <= '0';
elsif clk'event and clk = '1' then
if clk_en = '1' then
if status_wr_strobe = '1' then
break_detect <= '0';
elsif ((got_new_char AND is_break)) = '1' then
break_detect <= '1';
end if;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
rx_overrun <= '0';
elsif clk'event and clk = '1' then
if clk_en = '1' then
if status_wr_strobe = '1' then
rx_overrun <= '0';
elsif ((got_new_char AND internal_rx_char_ready)) = '1' then
rx_overrun <= '1';
end if;
end if;
end if;
end process;
process (clk, reset_n)
begin
if reset_n = '0' then
internal_rx_char_ready <= '0';
elsif clk'event and clk = '1' then
if clk_en = '1' then
if rx_rd_strobe_onset = '1' then
internal_rx_char_ready <= '0';
elsif got_new_char = '1' then
internal_rx_char_ready <= '1';
end if;
end if;
end if;
end process;
parity_error <= '0';
--_reg, which is an e_register
process (clk, reset_n)
begin
if reset_n = '0' then
unxxx108_out <= "0000000000";
elsif clk'event and clk = '1' then
if clk_en = '1' then
unxxx108_out <= unxxx108_in;
end if;
end if;
end process;
unxxx108_in <= A_WE_StdLogicVector ((do_start_rx = '1'),Std_Logic_Vector'(A_ToStdLogicVector('1') & A_ToStdLogicVector('1') & A_ToStdLogicVector('1') & A_ToStdLogicVector('1') & A_ToStdLogicVector('1') & A_ToStdLogicVector('1') & A_ToStdLogicVector('1') & A_ToStdLogicVector('1') & A_ToStdLogicVector('1') & A_ToStdLogicVector('1')),A_WE_StdLogicVector ((sample_enable = '1'),Std_Logic_Vector'(A_ToStdLogicVector(sync_rxd) & unxxx108_out(9 DOWNTO 1)),unxxx108_out));
rxd_shift_reg <= unxxx108_out;
shift_reg_start_bit_n <= unxxx108_out(0);
--vhdl renameroo for output signals
rx_char_ready <= internal_rx_char_ready;
end europa;
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
entity uart_regs is
port (
-- inputs:
signal address : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
signal break_detect : IN STD_LOGIC;
signal chipselect : IN STD_LOGIC;
signal clk : IN STD_LOGIC;
signal clk_en : IN STD_LOGIC;
signal framing_error : IN STD_LOGIC;
signal parity_error : IN STD_LOGIC;
signal read_n : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal rx_char_ready : IN STD_LOGIC;
signal rx_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
signal rx_overrun : IN STD_LOGIC;
signal tx_overrun : IN STD_LOGIC;
signal tx_ready : IN STD_LOGIC;
signal tx_shift_empty : IN STD_LOGIC;
signal write_n : IN STD_LOGIC;
signal writedata : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- outputs:
signal baud_divisor : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal dataavailable : OUT STD_LOGIC;
signal do_force_break : OUT STD_LOGIC;
signal irq : OUT STD_LOGIC;
signal readdata : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal readyfordata : OUT STD_LOGIC;
signal rx_rd_strobe : OUT STD_LOGIC;
signal status_wr_strobe : OUT STD_LOGIC;
signal tx_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
signal tx_wr_strobe : OUT STD_LOGIC
);
end entity uart_regs;
architecture europa of uart_regs is
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