uart.vhd

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--cyclone32: uart.vhd
--manual changes are highlighted by '###'

--Copyright (C) 1991-2002 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only to
--program PLD devices (but not masked PLD devices) from Altera.  Any other
--use of such megafunction design, net list, support information, device
--programming or simulation file, or any other related documentation or
--information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner.  Title to
--the intellectual property, including patents, copyrights, trademarks,
--trade secrets, or maskworks, embodied in any such megafunction design,
--net list, support information, device programming or simulation file, or
--any other related documentation or information provided by Altera or a
--megafunction partner, remains with Altera, the megafunction partner, or
--their respective licensors.  No other licenses, including any licenses
--needed under any third party's intellectual property, are provided herein.
--Copying or modifying any file, or portion thereof, to which this notice
--is attached violates this copyright.

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity uart_tx is 
        port (
              -- inputs:
                 signal baud_divisor : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal begintransfer : IN STD_LOGIC;
                 signal clk : IN STD_LOGIC;
                 signal clk_en : IN STD_LOGIC;
                 signal do_force_break : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal status_wr_strobe : IN STD_LOGIC;
                 signal tx_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal tx_wr_strobe : IN STD_LOGIC;

              -- outputs:
                 signal tx_overrun : OUT STD_LOGIC;
                 signal tx_ready : OUT STD_LOGIC;
                 signal tx_shift_empty : OUT STD_LOGIC;
                 signal txd : OUT STD_LOGIC
              );

end entity uart_tx;


architecture europa of uart_tx is
              signal baud_clk_en :  STD_LOGIC;
              signal baud_rate_counter :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal baud_rate_counter_is_zero :  STD_LOGIC;
              signal do_load_shifter :  STD_LOGIC;
              signal do_shift :  STD_LOGIC;
              signal internal_tx_ready :  STD_LOGIC;
              signal pre_txd :  STD_LOGIC;
              signal shift_done :  STD_LOGIC;
              signal tx_load_val :  STD_LOGIC_VECTOR (9 DOWNTO 0);
              signal tx_shift_reg_out :  STD_LOGIC;
              signal tx_shift_register_contents :  STD_LOGIC_VECTOR (9 DOWNTO 0);
              signal tx_wr_strobe_onset :  STD_LOGIC;
              signal unxxx48_in :  STD_LOGIC_VECTOR (9 DOWNTO 0);
              signal unxxx48_out :  STD_LOGIC_VECTOR (9 DOWNTO 0);

begin

  tx_wr_strobe_onset <= tx_wr_strobe AND begintransfer;
  tx_load_val <= Std_Logic_Vector'(A_ToStdLogicVector('1') & tx_data & A_ToStdLogicVector('0'));
  shift_done <= NOT (or_reduce(tx_shift_register_contents));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      do_load_shifter <= '0';
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        do_load_shifter <= (NOT internal_tx_ready) AND shift_done;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      internal_tx_ready <= '1';
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        if tx_wr_strobe_onset = '1' then 
          internal_tx_ready <= '0';
        elsif do_load_shifter = '1' then 
          internal_tx_ready <= '1';
        end if;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      tx_overrun <= '0';
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        if status_wr_strobe = '1' then 
          tx_overrun <= '0';
        elsif ((NOT internal_tx_ready AND tx_wr_strobe_onset)) = '1' then 
          tx_overrun <= '1';
        end if;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      tx_shift_empty <= '1';
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        tx_shift_empty <= internal_tx_ready AND shift_done;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      baud_rate_counter <= "00000000";
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        if ((baud_rate_counter_is_zero OR do_load_shifter)) = '1' then 
          baud_rate_counter <= baud_divisor;
        else
          baud_rate_counter <= baud_rate_counter - "00000001";
        end if;
      end if;
    end if;

  end process;

  baud_rate_counter_is_zero <= to_std_logic((baud_rate_counter = "00000000"));
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      baud_clk_en <= '0';
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        baud_clk_en <= baud_rate_counter_is_zero;
      end if;
    end if;

  end process;

  do_shift <= baud_clk_en AND (NOT shift_done) AND (NOT do_load_shifter);
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      pre_txd <= '1';
    elsif clk'event and clk = '1' then
      if ((NOT shift_done)) = '1' then 
        pre_txd <= tx_shift_reg_out;
      end if;
    end if;

  end process;

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      txd <= '1';
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        txd <= pre_txd AND NOT do_force_break;
      end if;
    end if;

  end process;

  --_reg, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      unxxx48_out <= "0000000000";
    elsif clk'event and clk = '1' then
      if clk_en = '1' then 
        unxxx48_out <= unxxx48_in;
      end if;
    end if;

  end process;

  unxxx48_in <= A_WE_StdLogicVector ((do_load_shifter = '1'),tx_load_val,A_WE_StdLogicVector ((do_shift = '1'),Std_Logic_Vector'(A_ToStdLogicVector('0') & unxxx48_out(9 DOWNTO 1)),unxxx48_out));
  tx_shift_register_contents <= unxxx48_out;
  tx_shift_reg_out <= unxxx48_out(0);
  --vhdl renameroo for output signals
  tx_ready <= internal_tx_ready;

end europa;


library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity uart_rx_stimulus_source is 
        port (
              -- inputs:
                 signal baud_divisor : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal clk_en : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;
                 signal rx_char_ready : IN STD_LOGIC;
                 signal rxd : IN STD_LOGIC;

              -- outputs:
                 signal source_rxd : OUT STD_LOGIC
              );

end entity uart_rx_stimulus_source;


architecture europa of uart_rx_stimulus_source is
component uart_tx is 
           port (
                 -- inputs:
                    signal baud_divisor : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal begintransfer : IN STD_LOGIC;
                    signal clk : IN STD_LOGIC;
                    signal clk_en : IN STD_LOGIC;
                    signal do_force_break : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                    signal status_wr_strobe : IN STD_LOGIC;
                    signal tx_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal tx_wr_strobe : IN STD_LOGIC;

                 -- outputs:
                    signal tx_overrun : OUT STD_LOGIC;
                    signal tx_ready : OUT STD_LOGIC;
                    signal tx_shift_empty : OUT STD_LOGIC;
                    signal txd : OUT STD_LOGIC
                 );
end component uart_tx;

component uart_rx_stimulus_source_character_source_rom_module is 
           port (
                 -- inputs:
                    signal address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
                    signal clk : IN STD_LOGIC;

                 -- outputs:
                    signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
                 );
end component uart_rx_stimulus_source_character_source_rom_module;

              signal aboriginal_start_pulse :  STD_LOGIC;
              signal address :  STD_LOGIC_VECTOR (9 DOWNTO 0);
              signal address_is_last :  STD_LOGIC;
              signal d1_aboriginal_start_pulse :  STD_LOGIC;
              signal d1_stim_data :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal d2_aboriginal_start_pulse :  STD_LOGIC;
              signal d3_aboriginal_start_pulse :  STD_LOGIC;
              signal d4_aboriginal_start_pulse :  STD_LOGIC;
              signal d5_aboriginal_start_pulse :  STD_LOGIC;
              signal d6_aboriginal_start_pulse :  STD_LOGIC;
              signal d7_aboriginal_start_pulse :  STD_LOGIC;
              signal d8_aboriginal_start_pulse :  STD_LOGIC;
              signal d9_aboriginal_start_pulse :  STD_LOGIC;
              signal delayed_unxxx81 :  STD_LOGIC;
              signal do_send_stim_data :  STD_LOGIC;
              signal internal_source_rxd :  STD_LOGIC;
              signal pickup_pulse :  STD_LOGIC;
              signal startup_pulse :  STD_LOGIC;
              signal stim_data :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              signal unused_empty :  STD_LOGIC;
              signal unused_overrun :  STD_LOGIC;
              signal unused_ready :  STD_LOGIC;
  constant simulating1 : boolean :=
-- exemplar translate_off
--###{
--    true OR
--###}
-- exemplar translate_on
    false;

begin

--exemplar translate_off
sim_generate:if simulating1 generate
    begin
      stimulus_transmitter : uart_tx
      port map(
        tx_shift_empty => unused_empty,
        txd => internal_source_rxd,
        tx_overrun => unused_overrun,
        tx_ready => unused_ready,
        clk_en => clk_en,
        status_wr_strobe => '0',
        tx_wr_strobe => '1',
        baud_divisor => baud_divisor,
        clk => clk,
        do_force_break => '0',
        tx_data => d1_stim_data,
        begintransfer => do_send_stim_data,
        reset_n => reset_n
      );



      process (clk, reset_n)
    begin
      if reset_n = '0' then
        d1_stim_data <= "00000000";
      elsif clk'event and clk = '1' then
        if do_send_stim_data = '1' then 
          d1_stim_data <= stim_data;
        end if;
      end if;

    end process;


      uart_rx_stimulus_source_character_source_rom : uart_rx_stimulus_source_character_source_rom_module
      port map(
        q => stim_data,
        address => address,
        clk => clk
      );



      process (clk, reset_n)
    begin
      if reset_n = '0' then
        address <= "0000000000";
      elsif clk'event and clk = '1' then
        if do_send_stim_data = '1' then 
          address <= address + "0000000001";
        end if;
      end if;

    end process;


      address_is_last <= to_std_logic((stim_data = "00000000"));

      --delayed_unxxx81, which is an e_register
    process (clk, reset_n)
    begin
      if reset_n = '0' then
        delayed_unxxx81 <= '0';
      elsif clk'event and clk = '1' then
        if clk_en = '1' then 
          delayed_unxxx81 <= rx_char_ready;
        end if;
      end if;

    end process;

    pickup_pulse <= NOT rx_char_ready AND delayed_unxxx81;

      process (clk, reset_n)
    begin
      if reset_n = '0' then
        aboriginal_start_pulse <= '1';
      elsif clk'event and clk = '1' then
        if clk_en = '1' then 
          aboriginal_start_pulse <= '0';
        end if;
      end if;

    end process;


      process (clk, reset_n)
    begin
      if reset_n = '0' then
        d1_aboriginal_start_pulse <= '0';
        d2_aboriginal_start_pulse <= '0';
        d3_aboriginal_start_pulse <= '0';