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	#define PORTE1 (*(_MEM Register*)(SIM_Register+0x12))
	#define DDRE (*(_MEM Register*)(SIM_Register+0x14))
	#define PEPAR (*(_MEM Register*)(SIM_Register+0x16))
	#define PORTF0 (*(_MEM Register*)(SIM_Register +0x18))
	#define PORTF1 (*(_MEM Register*)(SIM_Register+0x1a))
	#define DDRF (*(_MEM Register*)(SIM_Register+0x1c))
	#define PFPAR (*(_MEM Register*)(SIM_Register+0x1e))
	#define SYPCR (*(_MEM Sypcr*)(SIM_Register+0x20))
	#define PICR (*(_MEM Picr*)(SIM_Register+0x22))
	#define PITR (*(_MEM Pitr*)(SIM_Register+0x24))
	#define SWSR (*(_MEM int*)(SIM_Register+0x26))
	#define PORTC (*(_MEM Register*)(SIM_Register+0x40))
	#define CSPAR0 (*(_MEM Cspar*)(SIM_Register+0x44))
	#define CSPAR1 (*(_MEM Cspar*)(SIM_Register+0x46))
	#define CSBARBT (*(_MEM Csbar*)(SIM_Register+0x48) )
	#define CSORBT (*(_MEM Csor*)(SIM_Register+0x4a))
	#define CSBAR0 (*(_MEM Csbar*)(SIM_Register+0x4c))
	#define CSOR0 (*(_MEM Csor*)(SIM_Register+0x4e))
	#define CSBAR1 (*(_MEM Csbar*)(SIM_Register+0x50))
	#define CSOR1 (*(_MEM Csor*)(SIM_Register+0x52))
	#define CSBAR2 (*(_MEM Csbar*)(SIM_Register+0x54))
	#define CSOR2 (*(_MEM Csor*)(SIM_Register+0x56))
	#define CSBAR3 (*(_MEM Csbar*)(SIM_Register+0x58))
	#define CSOR3 (*(_MEM Csor*)(SIM_Register+0x5a))
	#define CSBAR4 (*(_MEM Csbar*)(SIM_Register+0x5c))
	#define CSOR4 (*(_MEM Csor*)(SIM_Register+0x5e))
	#define CSBAR5 (*(_MEM Csbar*)(SIM_Register+0x60))
	#define CSOR5 (*(_MEM Csor*)(SIM_Register+0x62))
	#define CSBAR6 (*(_MEM Csbar*)(SIM_Register+0x64))
	#define CSOR6 (*(_MEM Csor*)(SIM_Register+0x66))
	#define CSBAR7 (*(_MEM Csbar*)(SIM_Register+0x68))
	#define CSOR7 (*(_MEM Csor*)(SIM_Register+0x6a))
	#define CSBAR8 (*(_MEM Csbar*)(SIM_Register+0x6c))
	#define CSOR8 (*(_MEM Csor*)(SIM_Register+0x6e))
	#define CSBAR9 (*(_MEM Csbar*)(SIM_Register+0x70))
	#define CSOR9 (*(_MEM Csor*)(SIM_Register+0x72))
	#define CSBAR10 (*(_MEM Csbar*)(SIM_Register+0x74))
	#define CSOR10 (*(_MEM Csor*)(SIM_Register+0x76))

	/* Bitfields in RSR */

	#define TST bit0
	#define SYS bit1
	#define LOC bit2
	#define HLT bit4
	#define SW bit5
	#define POW bit6
	#define EXT bit7

	/* Bitfields in PORTE0, PORTE1 and PEPAR*/

	#define PE0 bit0
	#define PE1 bit1
	#define PE2 bit2
	#define PE3 bit3
	#define PE4 bit4
	#define PE5 bit5
	#define PE6 bit6
	#define PE7 bit7

	/* Bitfields in DDRE */

	#define DDE0 bit0
	#define DDE1 bit1
	#define DDE2 bit2
	#define DDE3 bit3
	#define DDE4 bit4
	#define DDE5 bit5
	#define DDE6 bit6
	#define DDE7 bit7

	/* Bitfields in PORTF0, PORTF1 and PFPAR*/

	#define PF0 bit0
	#define PF1 bit1
	#define PF2 bit2
	#define PF3 bit3
	#define PF4 bit4
	#define PF5 bit5
	#define PF6 bit6
	#define PF7 bit7

	/* Bitfields in DDRF */

	#define DDF0 bit0
	#define DDF1 bit1
	#define DDF2 bit2
	#define DDF3 bit3
	#define DDF4 bit4
	#define DDF5 bit5
	#define DDF6 bit6
	#define DDF7 bit7


	/* Bitfields in CSPAR0 */

	#define CSBOOT pr0
	#define CSPA01 pr1
	#define CSPA02 pr2
	#define CSPA03 pr3
	#define CSPA04 pr4
	#define CSPA05 pr5
	#define CSPA06 pr6

	/* Bitfields in CSPAR1  */

	#define CSPA10 pr0
	#define CSPA11 pr1
	#define CSPA12 pr2
	#define CSPA13 pr3
	#define CSPA14 pr4


	#endif
</code></pre>
 
<h4><a name="scim_h"> Single Chip Integration Module -- SCIM</a></h4>

<p>	The SCIM is a peripheral component found on the M68HC16Y1 component.
<pre><code>
	#ifndef SCIM_H
	#define SCIM_H 

	#ifdef _PAGE0
	#define _MEM @indir
	#else
	#ifdef _PAGEF
	#define _MEM
	#else 
	#define _MEM @far
	#endif
	#endif

	typedef struct
	{
	    unsigned bit0 :1;
	    unsigned bit1 :1;
	    unsigned bit2 :1;
	    unsigned bit3 :1;
	    unsigned bit4 :1;
	    unsigned bit5 :1;
	    unsigned bit6 :1;
	    unsigned bit7 :1;
	} Port;

	typedef struct
	{
	     unsigned STEXT :1;
	     unsigned STSCIM :1;
	     unsigned RSTEN :1;
	     unsigned SLOCK :1;
	     unsigned SLIMP :1;
	     unsigned NULL1  :2;
	     unsigned EDIV  :1;
	     unsigned Y     :6;
	     unsigned X     :1;
	     unsigned W     :1;
	} Syncr;

	typedef struct
	{
	     unsigned BMT :2;
	     unsigned BME :1;
	     unsigned HME :1;
	     unsigned SWT :2;
	     unsigned SWP :1;
	     unsigned SWE :1;
	}Sypcr; 

	typedef struct
	{
	     unsigned PIV   :8;
	     unsigned PIRQL :3;
	     unsigned NULL2  :5;
	} Picr;

	typedef struct
	{
	     unsigned PITM  :8;
	     unsigned PTP   :1;
	     unsigned NULL3  :7;
	}Pitr;

	typedef struct
	{
	     unsigned pr0 :2;
	     unsigned pr1 :2;
	     unsigned pr2 :2;
	     unsigned pr3 :2;
	     unsigned pr4 :2;
	     unsigned pr5 :2;
	     unsigned pr6 :2;
	     unsigned pr7 :2;
	} Cspar;

	typedef struct
	{
	     unsigned BLKSZ :3;
	     unsigned HIADDR :13;
	} Csbar;

	typedef struct
	{
	     unsigned AVEC :1;
	     unsigned IPL :3;
	     unsigned SPACE :2;
	     unsigned DSACK :4;
	     unsigned STRB :1;
	     unsigned RSW :2;
	     unsigned BYTE :2;
	     unsigned MODE :1;
	} Csor;

	#define SCIM_MCR (*(_MEM MCR_Register*)(SCIM_Register))
	#define SYNCR (*(_MEM Syncr*)(SCIM_Register+0x4))
	#define RSR (*(_MEM Register*)(SCIM_Register+0x6))
	#define SCIMTRE (*(_MEM Register*)(SCIM_Register+0x8))
	#define PORTA (*(_MEM Port *)(SCIM_Register+0xa))
	#define PORTB (*(_MEM Port *)(SCIM_Register+0xb))  
	#define PORTG (*(_MEM Port*)(SCIM_Register+0xc))  
	#define PORTH (*(_MEM Port *)(SCIM_Register+0xd))
	#define DDRG (*(_MEM Port *)(SCIM_Register+0xe)) 
	#define DDRH (*(_MEM Port *)(SCIM_Register+0xf)) 
	#define PORTE0 (*(_MEM Port*)(SCIM_Register+0x11))
	#define PORTE1 (*(_MEM Port*)(SCIM_Register+0x13)) 
	#define DDRAB (*(_MEM Port*)(SCIM_Register+0x14)) 
	#define DDRE (*(_MEM Register*)(SCIM_Register+0x15)) 
	#define PEPAR (*(_MEM Register*)(SCIM_Register+0x16)) 
	#define PORTF0 (*(_MEM Register*)(SCIM_Register +0x18)) 
	#define PORTF1 (*(_MEM Register*)(SCIM_Register+0x1a)) 
	#define DDRF (*(_MEM Register*)(SCIM_Register+0x1c)) 
	#define PFPAR (*(_MEM Register*)(SCIM_Register+0x1e)) 
	#define SYPCR (*(_MEM Sypcr*)(SCIM_Register+0x20)) 
	#define PICR  (*(_MEM Picr*)(SCIM_Register+0x22)) 
	#define PITR (*(_MEM Pitr*)(SCIM_Register+0x24))
	#define SWSR (*(_MEM int*)(SCIM_Register+0x26))
	#define PORTFE (*(_MEM Register*)(SCIM_Register+0x28))
	#define PFIVR (*(_MEM Register*)(SCIM_Register+0x2a))
	#define PFLVR (*(_MEM Register*)(SCIM_Register+0x2c))
	#define TSTMSRA (*(_MEM Register*)(SCIM_Register+0x30))
	#define TSTMSRB (*(_MEM Register*)(SCIM_Register+0x32))
	#define TSTSCA (*(_MEM char *)(SCIM_Register+0x34))
	#define TSTMCB (*(_MEM char *)(SCIM_Register+0x35))
	#define TSTRC (*(_MEM int *)(SCIM_Register+0x36))
	#define CREG (*(_MEM int *)(SCIM_Register+0x38))
	#define DREG (*(_MEM int *)(SCIM_Register+0x3a))
	#define PORTC (*(_MEM Register*)(SCIM_Register+0x40))
	#define CSPAR0 (*(_MEM Cspar*)(SCIM_Register+0x44))
	#define CSPAR1 (*(_MEM Cspar*)(SCIM_Register+0x46))
	#define CSBARBT (*(_MEM Csbar*)(SCIM_Register+0x48) )
	#define CSORBT (*(_MEM Csor*)(SCIM_Register+0x4a))
	#define CSBAR0 (*(_MEM Csbar*)(SCIM_Register+0x4c))
	#define CSOR0 (*(_MEM Csor*)(SCIM_Register+0x4e))
	#define CSBAR1 (*(_MEM Csbar*)(SCIM_Register+0x50))
	#define CSOR1 (*(_MEM Csor*)(SCIM_Register+0x52))
	#define CSBAR2 (*(_MEM Csbar*)(SCIM_Register+0x54))
	#define CSOR2 (*(_MEM Csor*)(SCIM_Register+0x56))
	#define CSBAR3 (*(_MEM Csbar*)(SCIM_Register+0x58))
	#define CSOR3 (*(_MEM Csor*)(SCIM_Register+0x5a))
	#define CSBAR4 (*(_MEM Csbar*)(SCIM_Register+0x5c))
	#define CSOR4 (*(_MEM Csor*)(SCIM_Register+0x5e))
	#define CSBAR5 (*(_MEM Csbar*)(SCIM_Register+0x60))
	#define CSOR5 (*(_MEM Csor*)(SCIM_Register+0x62))
	#define CSBAR6 (*(_MEM Csbar*)(SCIM_Register+0x64))
	#define CSOR6 (*(_MEM Csor*)(SCIM_Register+0x66))
	#define CSBAR7 (*(_MEM Csbar*)(SCIM_Register+0x68))
	#define CSOR7 (*(_MEM Csor*)(SCIM_Register+0x6a))
	#define CSBAR8 (*(_MEM Csbar*)(SCIM_Register+0x6c))
	#define CSOR8 (*(_MEM Csor*)(SCIM_Register+0x6e))
	#define CSBAR9 (*(_MEM Csbar*)(SCIM_Register+0x70))
	#define CSOR9 (*(_MEM Csor*)(SCIM_Register+0x72))
	#define CSBAR10 (*(_MEM Csbar*)(SCIM_Register+0x74))
	#define CSOR10 (*(_MEM Csor*)(SCIM_Register+0x76))

	/* Bitfields in RSR */

	#define TST bit0
	#define SYS bit1
	#define LOC bit2
	#define HLT bit4
	#define SW bit5
	#define POW bit6
	#define EXT bit7

	/* Bitfields in PORTE0, PORTE1 and PEPAR*/

	#define PE0 bit0
	#define PE1 bit1
	#define PE2 bit2
	#define PE3 bit3
	#define PE4 bit4
	#define PE5 bit5
	#define PE6 bit6
	#define PE7 bit7

	/* Bitfields in DDRE */

	#define DDE0 bit0
	#define DDE1 bit1
	#define DDE2 bit2
	#define DDE3 bit3
	#define DDE4 bit4
	#define DDE5 bit5
	#define DDE6 bit6
	#define DDE7 bit7

	/* Bitfields in PORTF0, PORTF1 and PFPAR*/

	#define PF0 bit0
	#define PF1 bit1
	#define PF2 bit2
	#define PF3 bit3
	#define PF4 bit4
	#define PF5 bit5
	#define PF6 bit6
	#define PF7 bit7

	/* Bitfields in DDRF */

	#define DDF0 bit0
	#define DDF1 bit1
	#define DDF2 bit2
	#define DDF3 bit3
	#define DDF4 bit4
	#define DDF5 bit5
	#define DDF6 bit6
	#define DDF7 bit7


	/* Bitfields in CSPAR0 */

	#define CSBOOT pr0
	#define CSPA01 pr1
	#define CSPA02 pr2
	#define CSPA03 pr3
	#define CSPA04 pr4
	#define CSPA05 pr5
	#define CSPA06 pr6

	/* Bitfields in CSPAR1  */

	#define CSPA10 pr0
	#define CSPA11 pr1
	#define CSPA12 pr2
	#define CSPA13 pr3
	#define CSPA14 pr4


	#endif
</code></pre>

 
<h4><a name="sram_h">Static RAM Module -- SRAM</a></h4>
<p>
	This module is found on the M68HC16Zx components.  It is not associated with 
another peripheral component found on the chip. There are 1K, 0x400, bytes of RAM in 
the SRAM module.
<pre><code>
	#ifndef SRAM_H
	#define SRAM_H

	#ifdef _PAGE0
	#define _MEM @indir
	#else
	#ifdef _PAGEF
	#define _MEM
	#else 
	#define _MEM @far
	#endif
	#endif

	typedef struct
	{
	     unsigned Nu :8;
	     unsigned RASP :2;
	     unsigned NULL1:1;
	     unsigned RCLK :1;
	     unsigned NULL2:3;
	     unsigned STOP :1;
	}Rammcr;

	#define RAMMCR (*(_MEM Rammcr*)(SRAM_Register + 0x00))
	#define RAMBAH (*(_MEM int*)(SRAM_Register + 0x04))
	#define RAMBAL (*(_MEM int*)(SRAM_Register + 0x06))

	#endif
</code></pre>
 
<h4><a name="tpuram_h">Timer Processor Unit RAM -- TPURAM</a></h4>

<p>	The Timer Processor Unit found on the M68HC16Y1 and other parts contains a 
block of RAM.  This RAM, if not used for the TPU, is available to the processor for 
memory storage.  This header file can be used to set-up access to the TPURAM.  There 
are 2K, 0x800, bytes of RAM in the TPURAM.
<pre><code>
	#ifndef TPURAM_H
	#define TPURAM_H 

	#ifdef _PAGE0
	#define _MEM @indir
	#else
	#ifdef _PAGEF
	#define _MEM
	#else 
	#define _MEM @far
	#endif
	#endif

	typedef struct
	{
	     unsigned NULLTPU0 :8;
	     unsigned RASP     :1;
	     unsigned NULLTPU1 :6;
	     unsigned STOPTPU  :1;
	}Trammcr;

	typedef struct
	{
	    unsigned RAMDS    :1;
	    unsigned NULLTPU3 :2;
	    unsigned AD11_23  :13;
	} Trambar;

	#define TRAMMCR (*(_MEM Trammcr*)(TPURAM_Register + 0x00))
	#define TRAMBAR (*(_MEM int*)(TPURAM_Register + 0x04))

	#endif
</code></pre>



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