spi.asm.txt

DSP串口通讯程序实现两个DSP之间的串口通讯

.bss 	DATA_IN, DATA_IN_LEN
.bss 	DATA_OUT_PTR,1
.bss 	DATA_OUT, DATA_OUT_LEN
TEST_MSG_BYTES 	.set 	20h
.bss 	TEST_MSG_PTR,1
.bss 	TEST_MSG, TEST_MSG_BYTES
.bss 	TEST_MSG_END,1
.bss 	NEW_BYTE_FLAG, 1
RCV_MSG_TYPE 		.set 	DATA_IN
RCV_BYTE_NO 		.set 	DATA_IN + 1
RCV_DATA_START 	.set 	DATA_IN + 2
PARAMS 			.usect 	"VARS", 020h
.bss 	VAR1, 1 			
.data
ST0_TEMP 			.word 0
ST1_TEMP 			.word 0
KICK_DOG 			.macro
LDP 			#00E0H
SPLK 		#055H, WDKEY
SPLK 		#0AAH, WDKEY
LDP 			#DATA_IN_PTR
.endm
.text
START
CLRC 		SXM 				;Clear Sign Extension Mode
CLRC 		OVM 				;Reset Overflow Mode
;Set Data Page pointer to page 1 of the peripheral frame
LDP 			#DP_PF1 			;Page DP_PF1 includes WET through EINT 
;frames
;initialize WDT registers
SPLK 		#06Fh, WDCR 	;clear WDFLAG, Disable WDT, set WDT for 
;1 second
;overflow (max)
SPLK 		#07h, RTICR 	;clear RTI Flag, set RTI for 1 second
;overflow (max)
;EVM 10MHz oscillator settings. (XTAL2 open, OSCBYP_=GND)
SPLK 		#00B1h,CKCR1 	;CLKIN(OSC)=10MHz, Mult by 2, Div by 1.
SPLK 		#00C3h,CKCR0 	;CLKMD=PLL Enable,SYSCLK=CPUCLK/2,
;Clear reset flag bits in SYSSR (PORRST, PLLRST, ILLRST, SWRST, WDRST)
LACL 		SYSSR 			;ACCL <= SYSSR
AND 			#00FFh 			;Clear upper 8 bits of SYSSR
SACL 		SYSSR 			;Load new value into SYSSR
;initialize B1 RAM to zero's.
LAR 			AR1,#B1_SADDR 	;AR1 <= B1 start address
MAR 			*,AR1 			;use B1 start address for next indirect
ZAC 			;ACC <= 0
RPT 	#(CONTEXT_MEM_PTR_BYTES+STATUS_INFO_BYTES+DATA_OUT_LEN+DATA_IN_LEN+2)
;set repeat counter for sizeof(.bss)-1 
;loops
SACL 		*+ 				;write zeros to B1 RAM
;initialize B2 RAM to zero's.
LAR 			AR1,#B2_SADDR 	;AR1 <= B2 start address
MAR 			*,AR1 			;use B2 start address for next indirect
ZAC 							;ACC <= 0
RPT 			#1fh 			;set repeat counter for 1fh+1=20h or 32 
;loops
SACL 		*+ 				;write zeros to B2 RAM
;initialize STATUS_INFO
LAR 			AR1,#STATUS_INFO ;AR1 <= STATUS_INFO start address
MAR 			*,AR1 
SPLK 		#01,*+ 			;STAT1 = 1
SPLK 		#02,*+ 			;STAT2 = 2
SPLK 		#03,*+ 			;STAT3 = 3
SPLK 		#04,*+ 			;STAT4 = 4
SPLK 		#05,*+ 			;STAT5 = 5
;initialize TEST_MSG
LAR 			AR1,#TEST_MSG 	;AR1 <= TEST_MSG start address
MAR	 		*,AR1
SPLK 		#03h,*+
SPLK 		#06h,*+
SPLK 		#02h,*+
SPLK 		#03h,*+
SPLK 		#01h,*+
SPLK 		#0Fh,*+
MAR 			*-
LDP 			#TEST_MSG_END
SAR 			AR1, TEST_MSG_END
LAR 			AR1, #TEST_MSG_PTR
SPLK 		#TEST_MSG, *
LDP 			#NEW_BYTE_FLAG
SPLK 		#1, NEW_BYTE_FLAG
;Initialize DSP for interrupts
LAR 			AR6,#IMR ;
LAR 			AR7,#IFR ;
MAR 			*,AR6
LACL 		#011h 			;Enable INT1 also! XINT1 high pri
SACL 		*,AR7 			;Enable interrupt 5 only (SPI low 
;priority)
LACL 		* 				;Clear IFR by reading and
SACL 		*,AR6 			;writing contents back into itself
;call SPI initialization routine
CALL 		INIT_SPI
LDP 			#DATA_IN_PTR
;Initialize RX and TX buffers
SPLK 		#DATA_IN, DATA_IN_PTR 	
;Reset RX buffer pointer
SPLK 		#DATA_OUT, DATA_OUT_PTR	
;Reset TX buffer pointer
SPLK 		#0FFH, DATA_OUT 
;Initialize default TX byte = 
;ACKnowledge
;Initialize and enable XINT1
LDP 			#DP_PF1
SPLK 		#01h, XINT1CR	;Enable XINT1, high pri, falling edge
;Enable DSP interrupts
CLRC 		INTM
MAIN
LDP 			#NEW_BYTE_FLAG
MAR 			*, AR5
LAR 			AR5, NEW_BYTE_FLAG 
;UPDATE AR5
BANZ 		MAIN,*
RD_MSG 
;Check if "send status info" bit is set in 1st rcvd byte (msg type).
LDP 			#NEW_BYTE_FLAG
SPLK 		#1, NEW_BYTE_FLAG 
;UPDATE FLAG, NEW BYTE HAS BEEN READ
RESET_RCV_BFR
B 			MAIN
;INIT_SPI
;DESCRIPTION: SPI initialization subroutine. This SR initializes
;the SPI for data stream transfer to a master SPI.
;The 240 SPI is configured for 8-bit transfers as a slave.
INIT_SPI
;initialize SPI in slave mode
LDP 			#DP_PF1
SPLK 		#008Fh,SPICCR	;Reset SPI by writing 1 to SWRST
SPLK 		#0004h,SPICTL	;Disable ints & TALK, normal clock, 
;MASTER mode
SPLK 		#007Fh, SPIBRR 	;Slowest baud rate for testing code
SPLK 		#0002h,SPIPC1
SPLK 		#0022h,SPIPC2	;Set SIMO & SOMI functions to serial I/O
SPLK 		#0040h,SPIPRI	;Set SPI interrupt to low priority.
								;For emulation purposes, allow the SPI
								;to continue after an XDS suspension.
								;HAS NO EFFECT ON THE ACTUAL DEVICE.
SPLK 		#0000h,SPISTS	;Clear the SPI interrupt status bits
;falling edge with no delay
SPLK 		#0047h,SPICCR	;Release SWRST, clock polarity 1, 8 bits
SPLK 		#0017h,SPICTL	;Enable TALK, ena SPI int, CLK ph 0, 
;MASTER mode
RET 							;Return to MAIN routine.
;XINT1_ISR
;DESCRIPTION: XINT1 interrupt service routine.
XINT1_ISR
SST 			#0, ST0_TEMP 	;Auto page-0 DP
SST 			#1, ST1_TEMP
LDP 			#CONTEXT_MEM_PTR
SACL 		CONTEXT_MEM_PTR
SACH 		CONTEXT_MEM_PTR+1
SAR 			AR0, CONTEXT_MEM_PTR+2
SAR 			AR6, CONTEXT_MEM_PTR+3
LDP 			#0
LACL 		IMR
LDP 			#CONTEXT_MEM_PTR
SACL 		CONTEXT_MEM_PTR+4
SEND_TEST_MSG
;Send data
LDP 			#TEST_MSG
LAR 			AR0, TEST_MSG_END;END OF MEM
LAR 			AR6, TEST_MSG_PTR
MAR 			*, AR6
LACL 		*+
SAR 			AR6, TEST_MSG_PTR
LDP 			#DP_PF1
SACL 		SPIDAT
CMPR 		2 				;Compare AR6 and AR0
BCND 		DEBOUNCE_SW, NTC
;PTR WITHIN RANGE?
LDP 			#TEST_MSG
LAR 			AR6, #TEST_MSG 	;RESET IT IF NOT
SAR 			AR6, TEST_MSG_PTR
DEBOUNCE_SW
LAR 			AR0, #0100h
DELAY2
LAR 			AR6, #03FFFh
MAR 			*, AR6
DELAY1 
BANZ 		DELAY1
MAR 			*, AR0
BANZ 		DELAY2
LDP 			#DP_PF1
WAIT	
BIT 			XINT1CR, BIT6
BCND 		HIGH, TC
B 			WAIT 			;Wait for XINT1 pin to goto a logic 0
HIGH 		LDP #0 			;Debounce switch by clearing pending 
;ints
LACL 		#01
SACL 		IFR
LDP 			#DP_PF1
SPLK 		#001h, XINT1CR 	;Clear transition detect
LDP 			#CONTEXT_MEM_PTR
LACL 		CONTEXT_MEM_PTR+4
LDP 			#0
SACL 		IMR
LDP 			#CONTEXT_MEM_PTR
LAR 			AR6, CONTEXT_MEM_PTR+3
LAR 			AR0, CONTEXT_MEM_PTR+2
LACC 		CONTEXT_MEM_PTR+1,16
ADDS 		CONTEXT_MEM_PTR
LDP 			#0
LST 			#1, ST1_TEMP
LST 			#0, ST0_TEMP
CLRC 		INTM
RET
;SPI_ISR
;DESCRIPTION: SPI interrupt service routine.
SPI_ISR
SST 			#0, ST0_TEMP 	;Auto page-0 DP
SST 			#1, ST1_TEMP
LDP 			#CONTEXT_MEM_PTR
SACL 		CONTEXT_MEM_PTR
SACH 		CONTEXT_MEM_PTR+1
SAR 			AR7, CONTEXT_MEM_PTR+2
SAR 			AR6, CONTEXT_MEM_PTR+3
LDP 			#0
LACL 		IMR
LDP 			#CONTEXT_MEM_PTR
SACL 		CONTEXT_MEM_PTR+4
OVER_RUN
LDP 			#DP_PF1 			;Page DP_PF1 includes SPI
BIT 			SPISTS, 8 		;Overrun flag (SPISTS.7) set?
BCND 		CLEAR_FLAG, TC 	;If set, clear & return
READ_SPI
LDP 			#DP_PF1 			;Page DP_PF1 includes SPI
LACC 		SPIBUF 			;Load rcvd byte into ACC
LDP 			#DATA_IN_PTR 	;Set data page pointer to B1 page
LAR 			AR7, DATA_IN_PTR;update RX ptr
MAR 			*, AR7
SACL 		*+
SAR 			AR7, DATA_IN_PTR;Set RX pointer to next entry
;DEBUG CODE
LDP 			#NEW_BYTE_FLAG
SPLK 		#0, NEW_BYTE_FLAG
SPI_DONE
LDP 			#CONTEXT_MEM_PTR
LACL 		CONTEXT_MEM_PTR+4
LDP 			#0
SACL 		IMR
LDP 			#CONTEXT_MEM_PTR
LAR 			AR6, CONTEXT_MEM_PTR+3
LAR 			AR7, CONTEXT_MEM_PTR+2
LACC 		CONTEXT_MEM_PTR+1,16
ADDS 		CONTEXT_MEM_PTR
LDP 			#0
LST 			#1, ST1_TEMP
LST 			#0, ST0_TEMP
CLRC 		INTM
RET
CLEAR_FLAG
SPLK 		#0H, SPISTS
B 			SPI_DONE
;Interrupt Vectors
; DESCRIPTION: Used by linker to place this section at the reset vector
;location.
.sect "vectors"
B 			START 			;reset
B 			XINT1_ISR 		;Int level 1, high priority ext int
B 			START 			;Int level 2 not used
B 			START 			;Int level 3 not used
B 			START 			;Int level 4 not used
B 			SPI_ISR 			;Int level 5, low priority SPI
2．主节点命令文件spi.cmd
MEMORY
{
PAGE 0: 							/* Program Memory Map forF240EVM
 									in MP mode */
VECS: org=0h, len=40h 			/* external */
EXT_PROG: org=40h, len=0FDC0h 	/* external */
PAGE 1: 							/* Data Memory Map forF240EVM */
B2: org=60h , len=20h 			/* internal DARAM */
B0: org=0200h, len=100h 		/* internal DARAM */
B1: org=0300h, len=100h 		/* internal DARAM */
EXT_SRAM: org=08000h, len=08000h
/* external SRAM */
}
SECTIONS
{
.text: 	> 	EXT_PROG 		PAGE 0
.data: 	> 	B2 				PAGE 1
.bss:	> 	B1 				PAGE 1
vectors > 	VECS 			PAGE 0
VARS 	> 	EXT_SRAM 		PAGE 1
}
3．	仿真器初始化命令文件F240evm.cmd
echo F240evm.CMD for F240 EVM
;Reset Memory Map
mr
;DATA MEMORY
ma 	0x00000,1,0x0060,ram 		;MMRs
ma 	0x00060,1,0x0020,ram 		;On-Chip RAM B2
ma 	0x00200,1,0x0100,ram 		;On-Chip RAM B0 if CNF=0
ma 	0x00300,1,0x0100,ram 		;On-Chip RAM B1
ma 	0x07010,1,0x0010,ioport 	;Peripheral - System Config & Control
ma 	0x07020,1,0x0010,ioport 	;Peripheral - WDT / RTI
ma 	0x07030,1,0x0010,ioport 	;Peripheral - ADC
ma 	0x07040,1,0x0010,ioport 	;Peripheral - SPI
ma 	0x07050,1,0x0010,ioport 	;Peripheral - SCI
ma 	0x07070,1,0x0010,ioport 	;Peripheral - Ext Ints
ma 	0x07090,1,0x0010,ioport 	;Peripheral - Digital I/O
ma 	0x07400,1,0x000D,ioport 	;Peripheral - Event Mgr GPT
ma 	0x07411,1,0x000C,ioport 	;Peripheral - Event Mgr CMP,PWM
ma 	0x07420,1,0x0007,ioport 	;Peripheral - Event Mgr CAP,QEP
ma 	0x0742C,1,0x0009,ioport 	;Peripheral - Event Mgr Int Cntl
; for EVM, external RAM is in memory map
ma 	0x08000,1,0x08000,ram 		;Ext SRAM
;PROGRAM MEMORY
ma 	0x00000,0,0x04000,RAM 		;Internal Program memory - FLASH
ma 	0x04000,0,0x0BE00,RAM 		;External Program memory - SRAM
ma 	0x0FE00,0,0x00100,RAM 		;Available if CNF=1 i.e. B0
;I/O MEMORY
ma 	0x0000,2,0x0008,WOM 		;I/O Memory Mapped DAC Registers
ma 	0x0008,2,0x0004,ROM 		;I/O Memory Mapped DIP Switches
ma 	0x000C,2,0x0004,WOM 		;I/O Memory Mapped LEDs
mem 	0x0200
mem1 	0x0300
mem2 	0x0060
wa 	(ST0&(0x03ff))>>9,INTM,d 	;INTM Int Mode Bit
wa 	(ST0&0x0f),DP,x
;SPI application note programs
take c:\dspcode\x240\f240evm\SPI_app\master\spi1.tak 
;final version - working
echo F240evm.CMD HAS BEEN LOADED
4．评估板调试文件spi1.tak
cd 	c:\dspcode\x240\f240evm\spi_app
load 	spi.out
;Serial Peripheral Interface (SPI) Registers
wa 			*0x07040, SPICCR 			;SPI Config Control Reg
wa 			*0x07041, SPICTL 			;SPI Operation Control Reg
wa 			*0x07042, SPISTS 			;SPI Status Reg
wa 			*0x07044, SPIBRR 			;SPI Baud rate control reg
wa 			*0x07046, SPIEMU 			;SPI Emulation buffer reg
wa 			*0x07047, SPIBUF 			;SPI Serial Input buffer reg
wa 			*0x07049, SPIDAT 			;SPI Serial Data reg
wa 			*0x0704D, SPIPC1 			;SPI Port control reg1
wa 			*0x0704E, SPIPC2 			;SPI Port control reg2
wa 			*0x0704F, SPIPRI 			;SPI Priority control reg
wa 			*0x07070, XINT1CR 			;XINT1 Control Register
wa 			*0x0701A, SYSSR 			;System Status Register
wa 			(ST0&(0x03ff))>>9,INTM,x 	;INTM Int Mode Bit
wa 			(ST0&0x0f),DP,x
wa 			(ST0&0x0f)*128,Base,x
wa 			(ST0>>13),ARP,x
WA 			TEST_MSG,,x
WA 			*TEST_MSG_PTR,,x
WA 			*TEST_MSG_END,,x
WA			DATA_IN,,x
WA 			DATA_IN_PTR,,x
WA 			*DATA_IN_PTR,,x
WA 			DATA_OUT,,x
WA 			DATA_OUT_PTR,,x
WA 			*DATA_OUT_PTR,,x
WA 			STATUS_INFO,,x
WA 			*STATUS_INFO,,x
WA 			*VAR1,,x
WA 			*NEW_BYTE_FLAG,,x
;ba XINT1_ISR
;ba SPI_ISR
ba 			RD_MSG
;BA VERIFY_CHECKSUM
MEM 			DATA_IN_PTR
MEM1 		DATA_OUT_PTR
MEM2 		TEST_MSG
MEM3 		STATUS_INFO
bl