s3c4510b.h

自己写的ARM移植代码

/* 
This file contains I/O address and related constants for the ArmAnywhereII board.
http://www.kitopen.net
http://bbs.edw.com.cn
*/

//#ifndef	INCARMh
#define	INCARMh

#define TARGET_ARM
/*
 * Local-to-Bus memory address constants:
 * the local memory address always appears at 0 locally;
 * it is not dual ported.
 */

#define LOCAL_MEM_LOCAL_ADRS	0x00000000	/* fixed */
#define LOCAL_MEM_BUS_ADRS	0x00000000	/* fixed */


#define BUS		BUS_TYPE_NONE


#define ARM_CPU_SPEED	50000000	/* CPU clocked at 16 MHz. The timer */
					/* speed is related to this */


/*************************************************************************
* changes made from here
*/

/*************************************************************************
* S3C4510B SPECIAL REGISTERS 
*
*/

#define ASIC_BASE  		0x3ff0000

/* Interrupt Control */

#define INT_CNTRL_BASE 		(ASIC_BASE+0x4000) /*Define base of all interrupt */

/*SYSTEM MANAGER REGISTERS */

#define ARM_SYSCFG			(ASIC_BASE+0x0000)
#define ARM_CLKCON  		(ASIC_BASE+0x3000)
#define ARM_EXTACON0  		(ASIC_BASE+0x3008)
#define ARM_EXTACON1  		(ASIC_BASE+0x300c)
#define ARM_EXTDBWTH  		(ASIC_BASE+0x3010)
#define ARM_ROMCON0  		(ASIC_BASE+0x3014)
#define ARM_ROMCON1  		(ASIC_BASE+0x3018)
#define ARM_ROMCON2  		(ASIC_BASE+0x301c)
#define ARM_ROMCON3  		(ASIC_BASE+0x3020)
#define ARM_ROMCON4  		(ASIC_BASE+0x3024)
#define ARM_ROMCON5  		(ASIC_BASE+0x3028)
#define ARM_DRAMCON0  		(ASIC_BASE+0x302c)
#define ARM_DRAMCON1  		(ASIC_BASE+0x3030)
#define ARM_DRAMCON2  		(ASIC_BASE+0x3034)
#define ARM_DRAMCON3  		(ASIC_BASE+0x3038)
#define ARM_REFEXTCON 		(ASIC_BASE+0x303c)

/* controller registers */
#define ARM_INTMODE 		((volatile unsigned long *)(ASIC_BASE+0x4000))
#define ARM_INTPEND 		((volatile unsigned long *)(ASIC_BASE+0x4004))
#define ARM_INTMASK 		((volatile unsigned long *)(ASIC_BASE+0x4008))
#define ARM_INTOFFSET 		((volatile unsigned long *)(ASIC_BASE+0x4024))
#define ARM_INTPENDTST 	    ((volatile unsigned long *)(ASIC_BASE+0x402c))

#define INT_DISABLE             0x1fffff

#define ARM_INTPRI0 		((volatile unsigned long *)(ASIC_BASE+0x400C))
#define ARM_INTPRI1 		((volatile unsigned long *)(ASIC_BASE+0x4010))
#define ARM_INTPRI2 		((volatile unsigned long *)(ASIC_BASE+0x4014))
#define ARM_INTPRI3 		((volatile unsigned long *)(ASIC_BASE+0x4018))
#define ARM_INTPRI4 		((volatile unsigned long *)(ASIC_BASE+0x401C))
#define ARM_INTPRI5 		((volatile unsigned long *)(ASIC_BASE+0x4020))

#define ARM_INTOSET_FIQ 	((volatile unsigned long *)(ASIC_BASE+0x4030))
#define ARM_INTOSET_IRQ 	((volatile unsigned long *)(ASIC_BASE+0x4034))

/*TIMER REGISTERS*/

#define ARM_TMOD            ((volatile unsigned long *)(ASIC_BASE+0x6000))
#define ARM_TDATA0          ((volatile unsigned long *)(ASIC_BASE+0x6004))
#define ARM_TDATA1          ((volatile unsigned long *)(ASIC_BASE+0x6008))
#define ARM_TCNT0           ((volatile unsigned long *)(ASIC_BASE+0x600C))
#define ARM_TCNT1           ((volatile unsigned long *)(ASIC_BASE+0x6010))       

 /* I/O Port Interface  */

#define ARM_IOPMOD 	((volatile unsigned long *)(ASIC_BASE+0x5000))
#define ARM_IOPCON  ((volatile unsigned long *)(ASIC_BASE+0x5004))
#define ARM_IOPDATA ((volatile unsigned long *)(ASIC_BASE+0x5008))

/* IIC Registers */
#define  ARM_IICCON  (ASIC_BASE+0xf000)
#define  ARM_IICBUF  (ASIC_BASE+0xf004)
#define  ARM_IICPS   (ASIC_BASE+0xf008)
#define  ARM_IICCNT  (ASIC_BASE+0xf00c)
/******UART Registers*******/
#define ARM_ULCON0 ((volatile unsigned *)0x03FFD000) //UART channel0 line control register

#define ARM_UCON0 ((volatile unsigned *)0x03FFD004) //UART channel0 control register

#define ARM_USTAT0 ((volatile unsigned *)0x03FFD008) //UART channel0 status register

#define ARM_UTXBUF0 ((volatile unsigned *)0x03FFD00c) //UART channel0 transimit holding register

#define ARM_URXBUF0 ((volatile unsigned *)0x03FFD010) //UART channel0 recieve buffer register

#define ARM_UBRDIV0 ((volatile unsigned *)0x03FFD014) //Baud rate divisor register0

/* definitions for the KS32C50100 DUART */

#define N_SIO_CHANNELS		N_ARM_UART_CHANNELS
#define N_UART_CHANNELS		N_ARM_UART_CHANNELS
#define N_ARM_UART_CHANNELS	2		/* number of ARM UART chans */
#define UART_REG_ADDR_INTERVAL	1		/* registers 4 bytes apart */
#define SERIAL_A_BASE_ADR	(ASIC_BASE+0xD000)/* UART A base address */
#define SERIAL_B_BASE_ADR	(ASIC_BASE+0xE000)/* UART B base address */


/*************************************************************************
*
* DRAM Memory Bank 0 area MAP for Exception vector table 
* and Stack, User code area. 
*
*/

#define DRAM_BASE  	0x0	/* Final start address of DRAM */
#define DRAM_LIMIT 	0x2000000
#define	RESET_DRAM_START	0x100000	/* Start of DRAM on power-up 1M*/
#define	RESET_ROM_START	0x0	/* Start od ROM on power-up */

/****************************************************************************
*
* Format of the Program Status Register 
*/

#define FBit 	 	0x40
#define IBit  	 	0x80
#define LOCKOUT  	0xC0 	/* Interrupt lockout value */
#define LOCK_MSK 	0xC0 	/* Interrupt lockout mask value */
#define MODE_MASK 	0x1F 	/* Processor Mode Mask */
#define UDF_MODE 	0x1B 	/* Undefine Mode(UDF) */
#define ABT_MODE 	0x17 	/* Abort Mode(ABT) */
#define SUP_MODE 	0x13 	/* Supervisor Mode (SVC) */
#define IRQ_MODE 	0x12 	/* Interrupt Mode (IRQ) */
#define FIQ_MODE 	0x11 	/* Fast Interrupt Mode (FIQ) */
#define USR_MODE 	0x10 	/* User Mode(USR) */

/*************************************************************************
* SYSTEM CLOCK 
*/

#define MHz 		 1000000

#define fMCLK_MHz 	 50000000 	/* 50MHz, KS32C50100*/
#define fMCLK 		 fMCLK_MHz/MHz

#define ARM_INT_NUM_LEVELS	21
#define ARM_INT_CSR_MODE	ARM_INTMODE
#define ARM_INT_CSR_PEND	ARM_INTPEND
#define ARM_INT_CSR_ENB	ARM_INTMASK
#define ARM_INT_CSR_DIS	ARM_INTMASK
#define ARM_INT_CSR_INTOFFSET	ARM_INTOFFSET
#define ARM_INT_CSR_INTOSET_IRQ			ARM_INTOSET_IRQ

#define ARM_INT_CSR_MASK	0x1fffff	

#define ARM_INT_MODE_IRQ	0x00

/* interrupt levels */
#define INT_LVL_EXTINT0		0	/* External Interrupt0 */
#define INT_LVL_EXTINT1		1	/* External Interrupt1 */
#define INT_LVL_EXTINT2		2	/* External Interrupt2 */
#define INT_LVL_EXTINT3		3	/* External Interrupt3 */
#define INT_LVL_UARTTX0		4	/* UART 0 Transmit Interrupt */
#define INT_LVL_UARTRX0		5	/* UART 0 Receive & Error Interrupt */
#define INT_LVL_UARTTX1		6	/* UART 1 Transmit Interrupt */
#define INT_LVL_UARTRX1		7	/* UART 1 Receive & Error Interrupt */
#define INT_LVL_GDMA0		8	/* GDMA channel 0 interrupt*/
#define INT_LVL_GDMA1		9	/* GDMA channel 1 interrupt */
#define INT_LVL_TIMER0		10	/* Timer 0 Interrupt */
#define INT_LVL_TIMER1		11	/* Timer 1 Interrupt  */
#define INT_LVL_HDLCTxA		12	/* HDLC channel A Tx interrupt*/
#define INT_LVL_HDLCRxA		13	/* HDLC channel A Rx interrupt*/
#define INT_LVL_HDLCTxB		14	/* HDLC channel B Tx interrupt*/
#define INT_LVL_HDLCRxB		15	/* HDLC channel B Rx interrupt*/
#define INT_LVL_BDMATx		16	/* Ethernet controller BDMA Tx Interrupt */
#define INT_LVL_BDMARx		17	/* Ethernet controller BDMA Rx Interrupt */
#define INT_LVL_MACTx		18	/* Ethernet controller MAC Tx Interrupt*/
#define INT_LVL_MACRx		19	/* Ethernet controller MAC Rx Interrupt */
#define INT_LVL_IIC			20	/* IIC -Bus Interrupt */

/* interrupt vectors */

#define INT_VEC_EXTINT0	 IVEC_TO_INUM(INT_LVL_EXTINT0)	/* External Interrupt0 */
#define INT_VEC_EXTINT1	 IVEC_TO_INUM(INT_LVL_EXTINT1)	/* External Interrupt1*/
#define INT_VEC_EXTINT2	 IVEC_TO_INUM(INT_LVL_EXTINT2)	/* External Interrupt2*/
#define INT_VEC_EXTINT3	 IVEC_TO_INUM(INT_LVL_EXTINT3)	/* External Interrupt3*/
#define INT_VEC_UARTTX0	 IVEC_TO_INUM(INT_LVL_UARTTX0)	/* UART 0 Transmit Interrupt */
#define INT_VEC_UARTRX0  IVEC_TO_INUM(INT_LVL_UARTRX0)	/* UART 0 Receive & Error Interrupt */
#define INT_VEC_UARTTX1  IVEC_TO_INUM(INT_LVL_UARTTX1)	/* UART 1 Transmit Interrupt */
#define INT_VEC_UARTRX1  IVEC_TO_INUM(INT_LVL_UARTRX1)	/* UART 1 Receive & Error Interrupt */
#define INT_VEC_GDMA0	 IVEC_TO_INUM(INT_LVL_GDMA0)	/* GDMA channel 0 interrupt*/
#define INT_VEC_GDMA1	 IVEC_TO_INUM(INT_LVL_GDMA1)	/* GDMA channel 0 interrupt*/
#define INT_VEC_TIMER0	 IVEC_TO_INUM(INT_LVL_TIMER0)	/* Timer 0 Interrupt  */
#define INT_VEC_TIMER1	 IVEC_TO_INUM(INT_LVL_TIMER1)	/* Timer 1 Interrupt */
#define INT_VEC_HDLCTxA	 IVEC_TO_INUM(INT_LVL_HDLCTxA)	/* HDLC channel A Tx interrupt */
#define INT_VEC_HDLCRxA  IVEC_TO_INUM(INT_LVL_HDLCRxA)	/* HDLC channel A Rx interrupt*/
#define INT_VEC_HDLCTxB	 IVEC_TO_INUM(INT_LVL_HDLCTxB)	/* HDLC channel B Tx interrupt*/
#define INT_VEC_HDLCRxB	 IVEC_TO_INUM(INT_LVL_HDLCRxB)	/* HDLC channel B Rx interrupt*/
#define INT_VEC_BDMATx	 IVEC_TO_INUM(INT_LVL_BDMATx)	/* Ethernet controller BDMA Tx Interrupt */
#define INT_VEC_BDMARx	 IVEC_TO_INUM(INT_LVL_BDMARx)	/* Ethernet controller BDMA Rx Interrupt */
#define INT_VEC_MACTx	 IVEC_TO_INUM(INT_LVL_MACTx)	/* Ethernet controller MAC Tx Interrupt*/
#define INT_VEC_MACRx	 IVEC_TO_INUM(INT_LVL_MACRx)	/* Ethernet controller MAC Rx Interrupt */
#define INT_VEC_IIC	 	 IVEC_TO_INUM(INT_LVL_IIC)	    /* IIC -Bus Interrupt */


/**********************************************************************************************************
* Cache Definitions
*
*/

#define NON_CACHE_REGION	0x4000000
#define ARM_CACHE_ENABLE		0x02
#define ARM_CACHE_4K			0x00
#define ARM_CACHE_8K			0x10
#define ARM_CACHE_MODE			0x30
#define ARM_WRITE_BUFF			0x04
#define ARM_TAGRAM				0x11000000


/*
 *
 * definitions for the  Timer:
 * two timers clocked from same source and with the same reload overhead
 */
#define ARM_TIMER_BASE	0x0A800000		/* Address of base of timer */
#define ARM_TIMER_SYS_TC_DISABLE	(TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define ARM_TIMER_SYS_TC_ENABLE	(TC_ENABLE  | TC_PERIODIC | TC_DIV16)
#define ARM_TIMER_AUX_TC_DISABLE	(TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define ARM_TIMER_AUX_TC_ENABLE	(TC_ENABLE  | TC_PERIODIC | TC_DIV16)

#define SYS_TIMER_CLK	(ARM_CPU_SPEED)	/* Frequency of counter/timer */
#define AUX_TIMER_CLK	(ARM_CPU_SPEED)	/* Frequency of counter/timer */

#define ARM_RELOAD_TICKS	3		/* three ticks to reload timer */

#define SYS_TIMER_CLEAR(x)	(ARM_TIMER_T1CLEAR(x))	/* sys Clk is timer 1  */
#define SYS_TIMER_CTRL(x)	(ARM_TIMER_T1CTRL(x))
#define SYS_TIMER_LOAD(x)	(ARM_TIMER_T1LOAD(x))
#define SYS_TIMER_VALUE(x)	(ARM_TIMER_T1VALUE(x))
#define ARM_TIMER_VALUE_MASK	0xFFFF
#define AUX_TIMER_CLEAR(x)	(ARM_TIMER_T2CLEAR(x))	/* aux Clk is timer 2  */
#define AUX_TIMER_CTRL(x)	(ARM_TIMER_T2CTRL(x))
#define AUX_TIMER_LOAD(x)	(ARM_TIMER_T2LOAD(x))
#define AUX_TIMER_VALUE(x)	(ARM_TIMER_T2VALUE(x))

#define SYS_TIMER_INT_LVL (INT_LVL_TIMER0)
#define AUX_TIMER_INT_LVL (INT_LVL_TIMER1)

/***********定义中断变量************/
#define ext0_int 0x00001
#define ext1_int 0x00002
#define ext2_int 0x00004
#define ext3_int 0x00008
/************定义全局变量*************/