📄 example.asm
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* bit 4 0: 0=IOPC4, 1=SPICLK
* bit 3 0: 0=IOPC3, 1=SPISOMI
* bit 2 0: 0=IOPC2, 1=SPISIMO
* bit 1 0: 0=IOPC1, 1=BIO*
* bit 0 0: 0=IOPC0, 1=W/R*
SPLK #0000000000000000b,MCRC ;group C pins
* ||||||||||||||||
* FEDCBA9876543210
* bit 15 0: reserved
* bit 14 0: 0=IOPF6, 1=IOPF6
* bit 13 0: 0=IOPF5, 1=TCLKINB
* bit 12 0: 0=IOPF4, 1=TDIRB
* bit 11 0: 0=IOPF3, 1=T4PWM/T4CMP
* bit 10 0: 0=IOPF2, 1=T3PWM/T3CMP
* bit 9 0: 0=IOPF1, 1=CAP6
* bit 8 0: 0=IOPF0, 1=CAP5/QEP4
* bit 7 0: 0=IOPE7, 1=CAP4/QEP3
* bit 6 0: 0=IOPE6, 1=PWM12
* bit 5 0: 0=IOPE5, 1=PWM11
* bit 4 0: 0=IOPE4, 1=PWM10
* bit 3 0: 0=IOPE3, 1=PWM9
* bit 2 0: 0=IOPE2, 1=PWM8
* bit 1 0: 0=IOPE1, 1=PWM7
* bit 0 0: 0=IOPE0, 1=CLKOUT
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Configure IOPC0 pin as an output
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LDP #DP_PF2 ;set data page
LACC #0100h ;ACC = 0100h
OR PCDATDIR ;OR in PCDATDIR register
SACL PCDATDIR ;store result to PCDATDIR
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Setup the software stack
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
stk_len .set 100 ;stack length
stk .usect "stack",stk_len ;reserve space for stack
LAR AR1, #stk ;AR1 is the stack pointer
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Setup timers 1 and 2, and the PWM configuration
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LDP #DP_EVA ;set data page
SPLK #0000h, T1CON ;disable timer 1
SPLK #0000h, T2CON ;disable timer 2
SPLK #0000000000000000b, GPTCONA
* ||||||||||||||||
* FEDCBA9876543210
* bit 15 0: reserved
* bit 14 0: T2STAT, read-only
* bit 13 0: T1STAT, read-only
* bit 12-11 00: reserved
* bit 10-9 00: T2TOADC, 00 = no timer2 event starts ADC
* bit 8-7 00: T1TOADC, 00 = no timer1 event starts ADC
* bit 6 0: TCOMPOE, 0 = Hi-z all timer compare outputs
* bit 5-4 00: reserved
* bit 3-2 00: T2PIN, 00 = forced low
* bit 1-0 00: T1PIN, 00 = forced low
;Timer 1: Configure to clock the PWM on PWM1 pin.
;Symmetric PWM, 20KHz carrier frequency, 25% duty cycle
SPLK #0000h, T1CNT ;clear timer counter
SPLK #pwm_half_per, T1PR ;set timer period
SPLK #0000h, DBTCONA ;deadband units off
SPLK #pwm_duty, CMPR1 ;set PWM duty cycle
SPLK #0000000000000010b, ACTRA
* ||||||||||||||||
* FEDCBA9876543210
* bit 15 0: space vector dir is CCW (don't care)
* bit 14-12 000: basic space vector is 000 (dont' care)
* bit 11-10 00: PWM6/IOPB3 pin forced low
* bit 9-8 00: PWM5/IOPB2 pin forced low
* bit 7-6 00: PWM4/IOPB1 pin forced low
* bit 5-4 00: PWM3/IOPB0 pin forced low
* bit 3-2 00: PWM2/IOPA7 pin forced low
* bit 1-0 10: PWM1/IOPA6 pin active high
SPLK #1000001000000000b, COMCONA
* ||||||||||||||||
* FEDCBA9876543210
* bit 15 1: 1 = enable compare operation
* bit 14-13 00: 00 = reload CMPRx regs on timer 1 underflow
* bit 12 0: 0 = space vector disabled
* bit 11-10 00: 00 = reload ACTR on timer 1 underflow
* bit 9 1: 1 = enable PWM pins
* bit 8-0 0's: reserved
SPLK #0000100001000000b, T1CON
* ||||||||||||||||
* FEDCBA9876543210
* bit 15-14 00: stop immediately on emulator suspend
* bit 13 0: reserved
* bit 12-11 01: 01 = continous-up/down count mode
* bit 10-8 000: 000 = x/1 prescaler
* bit 7 0: reserved in T1CON
* bit 6 1: TENABLE, 1 = enable timer
* bit 5-4 00: 00 = CPUCLK is clock source
* bit 3-2 00: 00 = reload compare reg on underflow
* bit 1 0: 0 = disable timer compare
* bit 0 0: reserved in T1CON
;Timer 2: configure to generate a 250ms periodic interrupt
SPLK #0000h, T2CNT ;clear timer counter
SPLK #timer2_per, T2PR ;set timer period
SPLK #1101011101000000b, T2CON
* ||||||||||||||||
* FEDCBA9876543210
* bit 15-14 11: stop immediately on emulator suspend
* bit 13 0: reserved
* bit 12-11 10: 10 = continous-up count mode
* bit 10-8 111: 111 = x/128 prescaler
* bit 7 0: T2SWT1, 0 = use own TENABLE bit
* bit 6 1: TENABLE, 1 = enable timer
* bit 5-4 00: 00 = CPUCLK is clock source
* bit 3-2 00: 00 = reload compare reg on underflow
* bit 1 0: 0 = disable timer compare
* bit 0 0: SELT1PR, 0 = use own period register
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Other setup
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;LED index initialization
LDP #LED_index ;set data page
SPLK #1h, LED_index ;initialize the LED index
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Setup the core interrupts
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LDP #0h ;set data page
SPLK #0h,IMR ;clear the IMR register
SPLK #111111b,IFR ;clear any pending core interrupts
SPLK #000100b,IMR ;enable desired core interrupts
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Setup the event manager interrupts
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LDP #DP_EVA ;set data page
SPLK #0FFFFh, EVAIFRA ;clear all EVA group A interrupts
SPLK #0FFFFh, EVAIFRB ;clear all EVA group B interrupts
SPLK #0FFFFh, EVAIFRC ;clear all EVA group C interrupts
SPLK #00000h, EVAIMRA ;enabled desired EVA group A interrupts
SPLK #00001h, EVAIMRB ;enabled desired EVA group B interrupts
SPLK #00000h, EVAIMRC ;enabled desired EVA group C interrupts
LDP #DP_EVB ;set data page
SPLK #0FFFFh, EVBIFRA ;clear all EVB group A interrupts
SPLK #0FFFFh, EVBIFRB ;clear all EVB group B interrupts
SPLK #0FFFFh, EVBIFRC ;clear all EVB group C interrupts
SPLK #00000h, EVBIMRA ;enabled desired EVB group A interrupts
SPLK #00000h, EVBIMRB ;enabled desired EVB group B interrupts
SPLK #00000h, EVBIMRC ;enabled desired EVB group C interrupts
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Enable global interrupts
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CLRC INTM ;enable global interrupts
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Main loop
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
loop:
NOP
B loop ;branch to loop
**********************************************************************
* I N T E R R U P T S E R V I C E R O U T I N E S *
**********************************************************************
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;GP Timer 2 period interrupt (core interrupt INT3)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
timer2_isr:
;Context save to the software stack
MAR *,AR1 ;ARP=stack pointer
MAR *+ ;skip one stack location (required)
SST #1, *+ ;save ST1
SST #0, *+ ;save ST0
SACH *+ ;save ACCH
SACL *+ ;save ACCL
;Clear the T2PINT interrupt flag
LDP #DP_EVA ;set data page
SPLK #00001h, EVAIFRB ;clear T2PINT flag
;Sequence the LED bank on the LF2407 EVM
LDP #LED_index ;set data page
OUT LED_index, LED ;light the LED
LACC LED_index,1 ;load LED index with left shift of 1
SACL LED_index ;store updated index
SUB #0010h ;subtract the mask
BCND done, LT ;branch if index not ready for reset
SPLK #1h, LED_index ;reset LED index to 1
done:
;Toggle the IOPC0 pin
LDP #DP_PF2 ;set data page
LACC #0001h ;ACC = 0001h
XOR PCDATDIR ;XOR the IOPC0 bit to toggle the pin
SACL PCDATDIR ;store result to PCDATDIR
;context restore from the software stack
MAR *, AR1 ;ARP = AR1
MAR *- ;SP points to last entry
LACL *- ;restore ACCL
ADD *-,16 ;restore ACCH
LST #0, *- ;restore ST0
LST #1, *- ;restore ST1, unskip one stack location
CLRC INTM ;re-enable interrupts
RET ;return from the interrupt
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