init860.s

mpc860串口编程

   #-------------------------------------------------------------------------
   # Program Option Register 1 (OR1): further BCSR definitions
   #
   # AM (Address Mask) = 0xFFFF+1b = We've masked the upper 17 bits which 
   #                                 represents a 128K block for the 4 PLDs
   #                                 on the target. 
   #
   # ATM (Address Type Mask) = 000 = ignore addr type codes as a part of the
   #                                 addr comparison.
   #
   # CSNT/SAM (Chip Select Negation Time) = 0 = CS/|WE/ are negated normally.
   #
   # ACS/G5LA,G5LS (Address To Chip-Select Setup) = 00 = CS/ is output at the
   #                                                     same time as the 
   #                                                     addr lines.
   #
   # BI/ (Burst Inhibit) = 1 = Drive BI/ asserted. This bank does not support
   #                           burst accesses.
   #
   # SCY (Cycle Length In Clocks) = 0001 = Add a 1 clock cycle wait state
   #
   # SETA (External Transfer Acknowledge) = 0 = TA/ is generated internally 
   #                                            by the memory controller 
   #                                            unless asserted earlier 
   #                                            externally.
   #
   # TRLX (Timing Relaxed) = 0 = Normal timing is generated by the GPCM.
   #
   # EHTR (Extended Hold Time On Read Accesses) = 0 = Normal timing is 
   #                                                  generated by the memory
   #                                                  controller
   #-------------------------------------------------------------------------

   oris     r5,r0,0xFFFF     # R5 holds the value temporarily
   ori      r5,r5,0x8110

   #------------------
   # Write the values
   #------------------

   stw        r5,OR1(r4)
   stw        r3,BR1(r4)

   #-------------------------------------------------------------------------
   # Program Base Register 2 (BR2): This bank defines the DRAM interface.
   #
   # BA (Base Address) = 0x0000+0b for a total of 17 bits. 17 bit base addr
   #                     represents a minumum 32K block size.
   #
   # AT (Address Type) = 000b = no restrictions to bank
   # PS (Port Size) = 00b = 32 bit port size
   # PARE (Parity Enable) =  0 = parity checking disabled
   # WP (Write Protect) = 0 = both read and write accesses are allowed
   # MS (Machine Select) = 10 = User Programable Machine A Selected
   # V (Valid Bit) =  1 = Valid bit set
   #-------------------------------------------------------------------------

   oris     r3,r0,0x0000       # R3 holds the value temporarily     
   ori      r3,r3,0x0081

   #-------------------------------------------------------------------------
   # Program Option Register 2 (OR2): DRAM definitions
   #
   # AM (Address Mask) = 0xFFC0+0b = We've masked the upper 10 bits which 
   #                                 represents a 4 Mbyte block the DRAM in 
   #                                 this address base. 
   #
   # ATM (Address Type Mask) = 000 = ignore addr type codes as a part of the
   #                                 addr comparison.
   #
   # CSNT/SAM (Chip Select Negation Time) = 0 = CS/|WE/ are negated normally.
   #
   # ACS/G5LA,G5LS (Address To Chip-Select Setup) = 10 = CS/ is a output a 
   #                                                     quarter of a clk 
   #                                                     later than the addr
   #                                                     lines.
   #
   # BI/ (Burst Inhibit) = 1 = Drive BI/ negated. This bank supports burst
   #                           accesses.
   #
   # SCY (Cycle Length In Clocks) = 0000 = Add no clock cycle wait states
   #
   # SETA (External Transfer Acknowledge) = 0 = TA/ is generated internally 
   #                                            by the memory controller 
   #                                            unless asserted earlier 
   #                                            externally.
   #
   # TRLX (Timing Relaxed) = 0 = Normal timing is generated by the GPCM.
   #
   # EHTR (Extended Hold Time On Read Accesses) = 0 = Normal timing is 
   #                                                  generated by the memory
   #                                                  controller
   #-------------------------------------------------------------------------

   oris     r5,r0,0xFFC0     # R5 holds the value temporarily
   ori      r5,r5,0x0800

   #------------------
   # Write the values
   #------------------

   stw      r5,OR2(r4)
   stw      r3,BR2(r4)

   #-----------------------
   # return from init_memc
   #-----------------------

   bclr  20,0    # jump unconditionally to effective address in Link
                 # register


#########################################################################
# Function: init_siu
#
# Description: Initializes the System Interface Unit
#
#  History:
#
#  4/28/98    jay      
#
#########################################################################			

init_siu:

   #-------------------------------------------------------------------------
   # Program the SIU Module Configuration Register (SIUMCR) register as 
   # follows:
   #
   # - EARB (External Arbitration) = 0 = Internal Arbitration is used.
   #
   # - EARP (External Arbitration Request Priority) = 000 = Ignored in
   #   particular configuration.
   #
   # - DS HW (Data Show Cycles) = 0 = Disable show cycles for all internal
   #   data cycles.
   #
   # - DBGC (Debug Pins Configuration) = 00 = see bit configuration 
   #   description in manual.
   #
   # - DBPC (Debug Port Pins Configuration) = 00 = see bit configuration
   #   description in manual.
   #
   # - FRC (FRZ/IRQ6 pin Configuration) = 1 = configure to be IRQ6.
   #
   # - DLK (Debug Register Lock) = 1 = Bits 8:15 are locked.
   #
   # - OPAR (Odd Parity) = 0 = Even selected. This bit ignored for this 
   #   application.
   #
   # - PNCS (Parity Enable For Non-memory Controller Regions) = 0 = parity 
   #   disabled
   #
   # - DPC (Data Parity Pins Configuration) = 1 = Configures DP(0:3)/IRQ(3:6)
   #   functions as DP(0:3).
   #
   # - MPRE (Multi-processors Reservation Enable) = 0 = Inter-processor
   #   communication protocol is disabled.
   #
   # - MLRC (Mult-Level Reservation Control) = 01 = RETRY/|KR/|IRQ4/|SPKROUT
   #   is tri-stated.
   #
   # - AEME (Asyncronous External Master Enable) = 1 = any assertion of 
   #   the AS/ pin is interpreted by the memory controller as an external
   #   asynchronous master initiating a transfer.
   #
   # - SEME (Synchronous External Master Enable) = 0 = Ignore the TS/ pin
   #
   # - BSC (Byte Select Configuration) = 0 = see bit configuration 
   #   description in user's manual.
   #
   # - GB5E (GPL_B(5) Enable) = 1 = GPL_B(5)/ of the memory controller 
   #   functionality is active.
   #
   # - B2DD (Bank 2 Double Drive) = 0 = CS2/ line is not reflected on 
   #   GPL_A2/|GPL_B2/.
   #
   # - B3DD (Bank 3 Double Drive) = 0 = CS3/ line is not reflected on 
   #   GPL_A3/|GPL_B3/.
   #
   #-------------------------------------------------------------------------

   lwz        r3,SIUMCR(r4) #  SIUMCR = The old value bitwize
                            #           ored with 0x00032640
   addis      r5,0,0x0003
   ori        r5,r5,0x2640
	or         r3,r3,r5
   stw        r3,SIUMCR(r4)

   #-------------------------------------------------------------------------
   # Program the Periodic Interrupt Status and Control Register (PISCR) as 
   # follows:
   #
   # - PS (Periodic Interrupt Request Level) = 1 = negate bit value by 
   #   writing a one to it.
   #
   # - PIE (Periodic Interrupt Enable) = 0 = Don't generate an interrupt when
   #   PS bit is asserted.
   #
   # - PITF (Periodic Interrupt Timer Freeze) = 1 = The periodic interrupt
   #   timer stops while freeze is asserted.
   #
   # - PTE (Periodic Timer Enable) = 0 = Disable
   #-------------------------------------------------------------------------

   addi        r3,0,0x0082     #  PISCR = 0x0082 (16bit register)
   sth         r3,PISCR(r4)

   #-----------------------
   # return from init_siu
   #-----------------------

   bclr  20,0           # jump unconditionally to effective address in Link
                        # register



#########################################################################
# Function: init_stack
#
# Description: 
#
#   This function initializes the monitor's stack.
#   NOTE:  This code is compiler-specific. Diab uses R1 as the stack pointer.
#   R1 is loaded with the "top of stack" address. This code should only be 
#   called during startup and during the exception recovery routines.
#
#
#  History:
#
#  4/28/98    jay      
#
#########################################################################			


init_stack:

   #------------------------------------------------------------------------
   # SP_INIT this value is defined in flash.lnx which is a linker 
   # file.
   #------------------------------------------------------------------------

   oris     r1,r0,__SP_INIT@h  
   ori      r1,r1,__SP_INIT@l

   #----------------------------------------------------------------------
   # load the stack pointer 72 bytes down from top of stack to ensure one
   # stack frame of safety margin. 
   #----------------------------------------------------------------------

   stwu  r0,-72(r1)      
                            
   bclr  20,0           # jump unconditionally to effective address in Link
                        # register




#########################################################################
# Function: flush_cache
#
# Description: 
#
#   This function was written in the case where a user wants to flush the
#   entire cache.
#
#  History:
#
#  4/28/98    jay
#  6/9/98     jay - Only one way was being flushed. The lwz instruction was 
#                   added to take advantage of the LRU bit in the cache as a
#                   mechanism to switch over to the other way on the 
#                   second pass through the cache.      
#
#########################################################################			

flush_cache:

   #-----------------------------
   # Flush the entire data cache
   #-----------------------------

   addi      r3,0,0       # Read 1 word per cache line for 800 lines
   addi      r4,0,256     # 2 ways, 128 sets per way

DCacheFlushLoop:

   addic.  r4,r4,-1                 # decrementer, set cc bit
   dcbf    0,r3                     # flush the line (must be done before
                                    # before lwz

   lwz     r5,0(r3)                 # access memory
   addi    r3,r3,16                 # next line
   bc      12,1,DCacheFlushLoop     # Branch if greater than 0

   #-------------------------
   # return from flush_cache
   #-------------------------

   bclr  20,0           # jump unconditionally to effective address in Link
                        # register


#########################################################################
# Function: init_cache_mmu
#
# Description: Initializes the Data/Instruction Caches and calls the 
#              init_mmu function.
#
#  History:
#
#  4/28/98    jay      
#
#########################################################################			


init_cache_mmu:

   mfspr    r30,LR        # Save the Link Register value

   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   # Cache Initialization. Note that the Instruction and Data cache will be
   # enabled after the MMU is programmed. Also keep in mind that, due to the 
   # reset exception. MSR(ir)[Instruction Address Translation] and MSR(dr)
   # [Data Address Translation] will be 0 or disabled. When initializing the
   # cache in a condition other than when an exception occurred, these two 
   # bits will need to be cleared first.
   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   # Initialize the Instruction Cache
   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                                  
   #-----------------------------------------------------------------------
   # Program the Instruction Cache Control and Status Register
   #
   # - IEN (Instruction Cache Enable Status Bit) = 0 = Disabled
   #
   # - CMD (Data Cache Commands) = 0A00 = Unlock all cache lines and ways
   #
   # - All other bits are status related and are read only
   #-----------------------------------------------------------------------

   addis    r3,0,CacheU