init860.s

mpc860串口编程

   # Program the Data Cache Control and Status Register
   #
   # - DEN (Data Cache Enable Status Bit) = 0 = Disabled
   #
   # - DFWT (Data Cache Force Writethrough) = 0 = Data cache is determined
   #   by MMU.
   #
   # - LES (Little Endian Swap) = 0 = Address of the Data and the Instruction
   #   Caches is the unchanged address from the core. No byte swapping is 
   #   done on the data and instruction caches external accesses.
   #
   # - CMD (Data Cache Commands) = 0100 = Data Cache Disable
   #
   # - All other bits are status related and are read only
   #-----------------------------------------------------------------------

   oris     r3,r0,CacheDisableCmd     # DCache Disable command
   ori      r3,r3,0
   mtspr    DC_CST,r3

   #----------------------------------------------
   # Load the IMMR register with the base address
   #----------------------------------------------

   oris     r4,r0,0xFF00       # IMMR base addr = 0x0FF00000
   mtspr    IMMR,r4

   #-----------------------------------------------------------------------
   # Program the System Protection Control Register with the following 
   # values:
   #
   # - SWTC (Software Watchdog Timer Count) = 0xFFFF = programmed to max
   #   count value.
   #
   # - BMT (Bus Monitor Timing) = 0xFF = Set to max timeout period.
   #
   # - BME (Bus Monitor Enable) = 1 = enabled.
   #
   # - SWF (Software Watchdog Freeze) = 1 = The software timer stops when
   #   freeze is asserted.
   #
   # - SWE (Software Watchdog Enabled) = 0 = disabled for now. User will 
   #   have to enable this in a non-debug application.
   #
   # - SWRI (Software Watchdog Reset/Interrupt Select) = 0 = Software 
   #   watchdog timeout causes a nonmaskable interrupt to the PowerPC core.
   #
   # - SWP (Software Watchdog Prescale) = 0 = It's not prescaled.
   #-----------------------------------------------------------------------

   oris     r3,r0,0xFFFF
   ori      r3,r3,0xFF88   # SYPCR = 0xFFFFFF88
   stw      r3,SYPCR(r4)    

   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   # UPM and Chip Select Programming Section
   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
   bl       init_memc

   #~~~~~~~~~~~~~~~~~~~~
   # Initialize the SIU
   #~~~~~~~~~~~~~~~~~~~~

   bl       init_siu

   #-------------------------------------------------------------------------
   # Program the Instruction Support Control Register (ICTRL). This is a 
   # debug related register and it's description can be found in the back
   # of the Development Support section of the user's manual. Basically the
   # only thing being programmed is ISCT_SER and it's value is 110b. This 
   # means that the core is not serialized (Normal mode) and show cycle will
   # be performed for all indirect changes in the program flow if show cycles
   # are enabled. In this application, it is disabled.
   #-------------------------------------------------------------------------

   oris     r3,r0,0x0000    
   ori      r3,r3,0x0006
   mtspr    ICTRL,r3

   #-------------------------------------------------------------------------
   # Program the Debug Enable Register (DER). This register provides the user
   # with the reason for entering into the debug mode. We want all conditions
   # to end up as an exception. We don't want to enter into debug mode for 
   # any condition. See the back of of the Development Support section of the 
   # MPC860 User Manual for a description of this register.
   #-------------------------------------------------------------------------

   oris     r3,r0,0x0000    
   mtspr    DER,r3         # write 0

   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   # Clocks, PLL and Power Programming
   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

   bl       init_clks

   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   # Initialize Instruction and Data Cache and MMU
   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

   bl       init_cache_mmu

   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   # Vector Interrupt Table Relocation to address 0x00000000
   #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

   bl       vector_reloc

   #~~~~~~~~~~~~~~~~~~~~
   # end of mpc8xx_init
   #~~~~~~~~~~~~~~~~~~~~

   mtspr    LR,r31      # restore original Link Register value 

   bclr     20,0        # jump unconditionally to effective address in Link
                        # register


#########################################################################
# Function: init_memc
#
# Description: This function initializes UPMA and chip selects for memory 
#              and I/O devices. Chip select 0 is assigned to the flash
#              device. Chip select 1 is assigned to the BCSR (Board Control
#              and Status Registers). UPMA is assigned to the DRAM.
#
#              Important Debug Note: When executing this code out of DRAM
#              with the SDS debugger, this routine MUST not be called! 
#              The debugger programs the UPMA for DRAM operation before 
#              downloading and executing this code. Programming the UPM 
#              tables while executing this code out of DRAM will crash the
#              debugging session.
#
#  History:
#
#  4/28/98    jay      
#
#########################################################################			

init_memc:

   #-----------------------------------------------------------------------
   # program UPM tables by writing to its 64 RAM locations. Note that 
   # initialization of UPM RAM must be done before the Base Register
   # initialization for DRAM. Otherwise, system will hang when refresh
   # starts.
   #-----------------------------------------------------------------------

   #----------------------------------------------------------------------
   # This section of code calculates the actual number of entries from the 
   # UPM table.
   #----------------------------------------------------------------------

   oris     r5,r0,UpmTable@ha     # point R5 to paramenter table
   ori      r5,r5,UpmTable@l

   oris     r6,r0,UpmTableEnd@ha  # point R6 to end paramenter table
   ori      r6,r6,UpmTableEnd@l

   sub        r7,r6,r5            # Get total # of bytes
   srawi      r7,r7,2             # divide by 4 to get actual # of entries

   addis      r6,0,0              # MCR Command: OP=Write, UPMA, MAD=0
        
   #--------------------------------------------------
   # Transfer the data from code memory to UPM memory
   #--------------------------------------------------

UpmWriteLoop:

   lwz        r3,0(r5)              # get data from table 
   stw        r3,MDR(r4)            # store the data to MD register
   
   stw        r6,MCR(r4)            # issue command to MCR register

   addi       r5,r5,4               # next entry in the table
   addi       r6,r6,1               # next MAD address

   cmp        r6,r7                 # done yet ?
   bc         12,0,UpmWriteLoop     # branch if less than


   #-------------------------------------------------------------------------
   # Load the MPTPR register. This is the pre-scaler value used to determine
   # by how much the BRGCLK (Baud Rate Generator Clock) is divided down 
   # before it enters the UPMA and UPMB Periodic Timer block. The output of
   # the UPMA/B Periodic Timer block determines, for this application, the 
   # DRAM refresh rate.
   #
   # The DRAM in this application is (1 Meg X 32) or (4 Meg X 8). The refresh 
   # rate required per row is 16msec. The access time is 60 nsec and the 
   # number of rows = 1024. There is one bank. The chosen BRGCLK freq is 
   # 24 Mhz. DFBRG in the System Clock and Reset Control Register (SCCR) is 
   # at it's default state of 00 which means that the BRGCLK 1:1 divide 
   # ratio. The prescaler (PTP) value is divide by 8 and the PTA value is 
   # 187 in the Machine A Mode Register (MAMR). I used the following formula
   # to figure out PTA.
   #
   # PTA = Refresh_Period * Number_of_beats_per_refresh_cycle
   #       -----------------------------------------------------------
   #       Number_of_Rows_to_refresh * T_BRG * MPTPR * Number_of_banks
   #
   # where:
   #
   # - PTA = Periodic Timer A filled in MAMR.
   # - Refresh_Period = The time (usually in msec) required to refresh a dram
   #                    bank.
   # - Number_of_beats_per_refresh_cycle = In this example 4.
   # - Number_of_rows_to_refresh = The number of rows in a dram bank.
   # - T_BRG = The cycle time of the BRG clock
   # - MPTPR =  The value of the periodic timer prescaler (2 to 64)
   # - Number_of_banks = Number of dram banks to refresh
   #
   # Here's the refresh clock stream:
   #
   #           ----------    -----------   -----------     ------------
   #  BRG Clk->| PTP    |--->|  PTA    |-->|   UPMA  |---->| # of dram|
   #           |        |    |         |   |         |     | banks    |
   #           ----------    -----------   -----------     ------------
   #
   # Here are the numbers used in this example:
   #
   #    PTA =        (16 E-3) * 4
   #          -------------------------  = 187.5 or 187 (round down gives
   #          1024 * (1/24 E6) * 8 * 1                   faster refresh  )
   #
   #-------------------------------------------------------------------------

   addi       r3,0,0x0800     # MPTPR = 0x0800 (16bit register)
   sth        r3,MPTPR(r4)

   #--------------------------------------------------------------------------
   # Load the Machine A Mode Register (MAMR). Program the following:
   #
   #  - PTA (Periodic Timer A Period) with 187 (0xBB). 
   #  - PTAE (Periodic Timer A) enabled
   #  - AMA (Address Multiplex Size A) bits = 010. This row/column addressing
   #    structure.
   #  - DSA (Disable Timer Period) = 01 = 2 cycle disable period
   #  - G0CLA (General Line 0 Control A) = A12. The address that is output
   #    to GPL0/
   #  - GPL_A4DIS (GPL_A4/ Output Line Disable) = 1
   #  - RLF (Read Loop Field A) = 0001 = The loop is executed 1 time
   #  - WLF (Write Loop Field A) = 0001 = The loop is executed 1 time
   #  - TLFA (Timer Loop Field A) = 0010 = The loop is executed 2 times
   #--------------------------------------------------------------------------

   oris     r3,r0,0xBBA2     
   ori      r3,r3,0x1114   # MAMR = 0xBBA21114
   stw      r3,MAMR(r4)

   #-------------------------------------------------------------------------
   # Finish the Memory Controller by initializing the Base Registers and the
   # Options Registers for the active memory banks
   #-------------------------------------------------------------------------

   #-------------------------------------------------------------------------
   # Base Register 0 (BR0): Bank 0 is assigned to the 2Mbyte (512K X 32) 
   #                        flash that resides on the MPC860 ADS board. The 
   #                        particulars are defined here as well as 
   #                        the UPM table.
   #
   # BA (Base Address) = 0x0280+0b for a total of 17 bits. 17 bit base addr
   #                     represents a minumum 32K block size.
   #
   # AT (Address Type) = 000b = no restrictions to bank
   # PS (Port Size) = 00b = 32 bit port size
   # PARE (Parity Enable) =  0 = parity checking disabled
   # WP (Write Protect) = 0 = both read and write accesses are allowed
   # MS (Machine Select) = 00 = General Purpose Chip Select machine Selected
   # V (Valid Bit) =  1 = Valid bit set
   #-------------------------------------------------------------------------

   oris     r3,r0,0x0280   # R3 holds the value temporarily
   ori      r3,r3,0x0001

   #-------------------------------------------------------------------------
   # Option Register 0 (OR0): further flash definitions
   #
   # AM (Address Mask) = 0xFFE0+0b = We've masked the upper 11 bits which 
   #                                 which defines a 2 Mbyte memory block.
   #
   # ATM (Address Type Mask) = 000 = ignore addr type codes as a part of the
   #                                 addr comparison.
   #
   # CSNT/SAM (Chip Select Negation Time) = 1 = CS/|WE/ are negated a quarter
   #                                            of a clock early.
   #
   # ACS/G5LA,G5LS (Address To Chip-Select Setup) = 10 = CS/ is a output a 
   #                                                     quarter of a clk 
   #                                                     later than the addr
   #                                                     lines.
   #
   # BI/ (Burst Inhibit) = 1 = Drive BI/ asserted. This bank does not support
   #                           burst accesses.
   #
   # SCY (Cycle Length In Clocks) = 0101 = Add a 5 clock cycle wait state
   #
   # SETA (External Transfer Acknowledge) = 0 = TA/ is generated internally 
   #                                            by the memory controller 
   #                                            unless asserted earlier 
   #                                            externally.
   #
   # TRLX (Timing Relaxed) = 1 = Relaxed timing is generated by the GPCM.
   #
   # EHTR (Extended Hold Time On Read Accesses) = 0 = Normal timing is 
   #                                                  generated by the memory
   #                                                  controller
   #-------------------------------------------------------------------------

   oris     r5,r0,0xFFE0     # R5 holds the value temporarily
   ori      r5,r5,0x0954   

   #------------------------------------------------------------------------
   # It's important to note the order in which OR0 and BR0 are programmed.
   # When coming out of reset and CS0 is the global chip select, OR0 MUST be 
   # programmed AFTER BR0. In all other cases BRx would be programmed after
   # ORx.
   #------------------------------------------------------------------------

   #------------------
   # Write the values
   #------------------

   stw        r3,BR0(r4)
   stw        r5,OR0(r4)

   #-------------------------------------------------------------------------
   # Program Base Register 1 (BR1): This section further defines the inter-
   #                                face with the Board Control Status 
   #                                Registers (BCSR).There are 4 Programmable
   #                                Logic chips on the ADS board.
   #
   # BA (Base Address) = 0x0210+0b for a total of 17 bits. 17 bit base addr
   #                     represents a minumum 32K block size.
   #
   # AT (Address Type) = 000b = no restrictions to bank
   # PS (Port Size) = 00b = 32 bit port size
   # PARE (Parity Enable) =  0 = parity checking disabled
   # WP (Write Protect) = 0 = both read and write accesses are allowed
   # MS (Machine Select) = 00 = General Purpose Chip Select machine Selected
   # V (Valid Bit) =  1 = Valid bit set
   #-------------------------------------------------------------------------

   oris     r3,r0,0x0210     # R3 holds the value temporarily
   ori      r3,r3,0x0001