func.c

一个在mck2407板上控制无刷电机恒速运行的程序

#include    "f2407_c.h" 
#include	"var.h" 
#include 	"math.h"


/*** Constant Definitions ***/
#define         timer2_per    5000     /*  timer2 period with a 1/128
                                       timer prescaler and 40MHz CPUCLK */
#define PI 		3.1415926
unsigned int adc_res;
unsigned int dir=0; 
unsigned int ldd=0;
unsigned int PWM_DUTY=1500;


/****************************** MAIN ROUTINE ***************************/
void ini(void)
{

/*** Configure the System Control and Status registers ***/
    *SCSR1 = 0x00FD;
/*
 bit 15        0:      reserved
 bit 14        0:      CLKOUT = CPUCLK
 bit 13-12     00:     IDLE1 selected for low-power mode
 bit 11-9      000:    PLL x4 mode
 bit 8         0:      reserved
 bit 7         1:      1 = enable ADC module clock
 bit 6         1:      1 = enable SCI module clock
 bit 5         1:      1 = enable SPI module clock
 bit 4         1:      1 = enable CAN module clock
 bit 3         1:      1 = enable EVB module clock
 bit 2         1:      1 = enable EVA module clock
 bit 1         0:      reserved
 bit 0         1:      clear the ILLADR bit
*/

    *SCSR2 = (*SCSR2 | 0x000B) & 0x000F;
/*
 bit 15-6      0's:    reserved
 bit 5         0:      do NOT clear the WD OVERRIDE bit
 bit 4         0:      XMIF_HI-Z, 0=normal mode, 1=Hi-Z'd
 bit 3         1:      disable the boot ROM, enable the FLASH
 bit 2     no change   MP/MC* bit reflects state of MP/MC* pin
 bit 1-0      11:      11 = SARAM mapped to prog and data
*/


/*** Disable the watchdog timer ***/
    *WDCR  = 0x00E8;
/*
 bits 15-8     0's:     reserved
 bit 7         1:       clear WD flag
 bit 6         1:       disable the dog
 bit 5-3       101:     must be written as 101
 bit 2-0       000:     WDCLK divider = 1
*/


/*** Setup external memory interface for LF2407 EVM ***/
    WSGR = 0x0040;
/*
 bit 15-11     0's:    reserved
 bit 10-9      00:     bus visibility off
 bit 8-6       001:    1 wait-state for I/O space
 bit 5-3       000:    0 wait-state for data space
 bit 2-0       000:    0 wait state for program space
*/


/*** Setup shared I/O pins ***/
    *MCRA = 0x0fc0;                     /* group A pins */
/*
 bit 15        0:      0=IOPB7,     1=TCLKINA
 bit 14        0:      0=IOPB6,     1=TDIRA
 bit 13        0:      0=IOPB5,     1=T2PWM/T2CMP
 bit 12        0:      0=IOPB4,     1=T1PWM/T1CMP
 bit 11        1:      0=IOPB3,     1=PWM6
 bit 10        1:      0=IOPB2,     1=PWM5
 bit 9         1:      0=IOPB1,     1=PWM4
 bit 8         1:      0=IOPB0,     1=PWM3
 bit 7         1:      0=IOPA7,     1=PWM2
 bit 6         1:      0=IOPA6,     1=PWM1
 bit 5         0:      0=IOPA5,     1=CAP3
 bit 4         0:      0=IOPA4,     1=CAP2/QEP2
 bit 3         0:      0=IOPA3,     1=CAP1/QEP1
 bit 2         0:      0=IOPA2,     1=XINT1
 bit 1         0:      0=IOPA1,     1=SCIRXD
 bit 0         0:      0=IOPA0,     1=SCITXD
*/

    *MCRB = 0xFE00;                     /* group B pins */
/*
 bit 15        1:      0=reserved,  1=TMS2 (always write as 1)
 bit 14        1:      0=reserved,  1=TMS  (always write as 1)
 bit 13        1:      0=reserved,  1=TD0  (always write as 1)
 bit 12        1:      0=reserved,  1=TDI  (always write as 1)
 bit 11        1:      0=reserved,  1=TCK  (always write as 1)
 bit 10        1:      0=reserved,  1=EMU1 (always write as 1)
 bit 9         1:      0=reserved,  1=EMU0 (always write as 1)
 bit 8         0:      0=IOPD0,     1=XINT2/ADCSOC
 bit 7         0:      0=IOPC7,     1=CANRX
 bit 6         0:      0=IOPC6,     1=CANTX
 bit 5         0:      0=IOPC5,     1=SPISTE
 bit 4         0:      0=IOPC4,     1=SPICLK
 bit 3         0:      0=IOPC3,     1=SPISOMI
 bit 2         0:      0=IOPC2,     1=SPISIMO
 bit 1         0:      0=IOPC1,     1=BIO*
 bit 0         0:      0=IOPC0,     1=W/R*
*/

    *MCRC = 0x0000;                     /* group C pins */
/*
 bit 15        0:      reserved
 bit 14        0:      0=IOPF6,     1=IOPF6
 bit 13        0:      0=IOPF5,     1=TCLKINB
 bit 12        0:      0=IOPF4,     1=TDIRB
 bit 11        0:      0=IOPF3,     1=T4PWM/T4CMP
 bit 10        0:      0=IOPF2,     1=T3PWM/T3CMP
 bit 9         0:      0=IOPF1,     1=CAP6
 bit 8         0:      0=IOPF0,     1=CAP5/QEP4
 bit 7         0:      0=IOPE7,     1=CAP4/QEP3
 bit 6         0:      0=IOPE6,     1=PWM12
 bit 5         0:      0=IOPE5,     1=PWM11
 bit 4         0:      0=IOPE4,     1=PWM10
 bit 3         0:      0=IOPE3,     1=PWM9
 bit 2         0:      0=IOPE2,     1=PWM8
 bit 1         0:      0=IOPE1,     1=PWM7
 bit 0         0:      0=IOPE0,     1=CLKOUT    
*/


/*** Configure PA5,PA4,PA3 pin as input ***/
    *PADATDIR = *PADATDIR&0xc7ff;


/*** Setup timers 1 and 2, and the PWM configuration ***/
    *T1CON = 0x0000;                    /* disable timer 1 */
    *T2CON = 0x0000;                    /* disable timer 2 */

    *GPTCONA = 0x0000;                  /* configure GPTCONA */
/*     
 bit 15        0:      reserved
 bit 14        0:      T2STAT, read-only
 bit 13        0:      T1STAT, read-only
 bit 12-11     00:     reserved
 bit 10-9      00:     T2TOADC, 00 = no timer2 event starts ADC
 bit 8-7       00:     T1TOADC, 00 = no timer1 event starts ADC
 bit 6         0:      TCOMPOE, 0 = Hi-z all timer compare outputs
 bit 5-4       00:     reserved
 bit 3-2       00:     T2PIN, 00 = forced low
 bit 1-0       00:     T1PIN, 00 = forced low
*/


/* Timer 1: configure to clock the PWM on PWM1 pin */
/* Symmetric PWM, 20KHz carrier frequency, 25% duty cycle */
    *T1CNT = 0x0000;                    /* clear timer counter */
    *T1PR = pwm_half_per;               /* set timer period */
    *DBTCONA = 0x0000;                  /* deadband units off */
    *CMPR3=*CMPR2=*CMPR1=PWM_DUTY;                  /* set PWM1 duty cycle */ 
    
    *ACTRA = 0x0fff;                    /* PWM1 pin set active high */     
/*
 bit 15        0:      space vector dir is CCW (don't care)
 bit 14-12     000:    basic space vector is 000 (dont' care)
 bit 11-10     01:     PWM6/IOPB3 pin active low
 bit 9-8       10:     PWM5/IOPB2 pin active high
 bit 7-6       01:     PWM4/IOPB1 pin active low
 bit 5-4       10:     PWM3/IOPB0 pin active high
 bit 3-2       01:     PWM2/IOPA7 pin active low
 bit 1-0       10:     PWM1/IOPA6 pin active high
*/

     *COMCONA = 0x8200;                 /* configure COMCON register */
/*
 bit 15        1:      1 = enable compare operation
 bit 14-13     00:     00 = reload CMPRx regs on timer 1 underflow
 bit 12        0:      0 = space vector disabled
 bit 11-10     00:     00 = reload ACTR on timer 1 underflow
 bit 9         1:      1 = enable PWM pins
 bit 8-0       0's:    reserved
*/


     *T1CON = 0x0840;                   /* configure T1CON register */
/*     
 bit 15-14     00:     stop immediately on emulator suspend
 bit 13        0:      reserved
 bit 12-11     01:     01 = continous-up/down count mode
 bit 10-8      000:    000 = x/1 prescaler
 bit 7         0:      reserved in T1CON
 bit 6         1:      TENABLE, 1 = enable timer
 bit 5-4       00:     00 = CPUCLK is clock source
 bit 3-2       00:     00 = reload compare reg on underflow
 bit 1         0:      0 = disable timer compare
 bit 0         0:      reserved in T1CON
*/


/* Timer 2: configure to generate a 250ms periodic interrupt */
    *T2CNT = 0x0000;                    /* clear timer counter */
    *T2PR = timer2_per;                 /* set timer period */

    *T2CON = 0xD740;                    /* configure T2CON register */
/*     
 bit 15-14     11:     stop immediately on emulator suspend
 bit 13        0:      reserved
 bit 12-11     10:     10 = continous-up count mode
 bit 10-8      111:    111 = x/128 prescaler
 bit 7         0:      T2SWT1, 0 = use own TENABLE bit
 bit 6         1:      TENABLE, 1 = enable timer
 bit 5-4       00:     00 = CPUCLK is clock source
 bit 3-2       00:     00 = reload compare reg on underflow
 bit 1         0:      0 = disable timer compare
 bit 0         0:      SELT1PR, 0 = use own period register
*/


/*** Setup the core interrupts ***/
    *IMR = 0x0000;                      /* clear the IMR register */
    *IFR = 0x003F;                      /* clear any pending core interrupts */
    *IMR = 0x0007;                      /* enable desired core interrupts (in2,in3)*/

/*** Setup the event manager interrupts ***/
    *EVAIFRA = 0xFFFF;                  /* clear all EVA group A interrupts */
    *EVAIFRB = 0xFFFF;                  /* clear all EVA group B interrupts */
    *EVAIFRC = 0xFFFF;                  /* clear all EVA group C interrupts */
    *EVAIMRA = 0x0200;                  /* enable desired EVA group A interrupts */
    *EVAIMRB = 0x0001;                  /* enable desired EVA group B interrupts ENABLE TIME2*/
    *EVAIMRC = 0x0000;                  /* enable desired EVA group C interrupts */

    *EVBIFRA = 0xFFFF;                  /* clear all EVB group A interrupts */
    *EVBIFRB = 0xFFFF;                  /* clear all EVB group B interrupts */
    *EVBIFRC = 0xFFFF;                  /* clear all EVB group C interrupts */
    *EVBIMRA = 0x0000;                  /* enable desired EVB group A interrupts */
    *EVBIMRB = 0x0000;                  /* enable desired EVB group B interrupts */
    *EVBIMRC = 0x0000;                  /* enable desired EVB group C interrupts */

}

void init_adc(void)
{
	*T4CNT=0x0000l;
	*T4CON=0x170c;
	*T4PR=0x75;
	*GPTCONB=0x400;
	*EVBIFRB=0xffff;
	*ADCTRL1=0x10;
	*ADCTRL2=0x8404;
	*MAX_CONV=0x03;
	*CHSELSEQ1=0x3210;
}

void adc_soc(void)
{
	*T4CON=*T4CON|0x40;
}
	                                      
void interrupt adcint(void)
{
	asm("	clrc SXM");
	adc_res=*RESULT2>>6;
	if(adc_res>0x2cf)adc_res=0x2cf;
	if(adc_res<0x38)adc_res=0x38;
	*ADCTRL2|=0x4200;
	PWM_DUTY=1200+(adc_res-0x38);
	if(PWM_DUTY<1200)PWM_DUTY=1200;
	if(PWM_DUTY>1800)PWM_DUTY=1800;
	asm(" CLRC INTM");
}

void stop(void)
{
	unsigned int i,j;
	*ACTRA=0x0333;
	for(i=0;i<10;i++)
	for(j=0;j<40000;j++);
}
	
	



/********************** INTERRUPT SERVICE ROUTINES *********************/
interrupt void timer2_isr(void)
{
     asm(" SETC INTM");
     
     *EVAIFRB = *EVAIFRB & 0x0001;      /* clear T2PINT flag */
     
     if(time_cnt==0)
     {
 	 	ldd=!ldd;
 	 	/*
 	 	stop();
 	 	dir=!dir;
 	 	*/
 	 	time_cnt=C_TIME;
 	 }
 	 time_cnt--;
 	 
 	 asm(" CLRC INTM");
} 


/********************** interrupt 2 service routine************************/
interrupt void inter2_isr(void)
{
	/*asm(" SETC INTM");*/
	*EVAIFRA = *EVAIFRA & 0x0200;
	hall=*PADATDIR&0x0038;
	if(*PIVR==0x0029)             /*time1 overbelow interrupt*/
	{
		switch(hall)
		{
			case 0x08:    /*PWM1-PWM6   ANC*/
			{   
				if(dir==0)
				*ACTRA=0x03fd;
				else
				*ACTRA=0x0df3; 
				break;
			}
			case 0x18:	/*PWM3-PWM6     BNC*/
			{
				if(dir==0)
				*ACTRA=0x03df;
				else
				*ACTRA=0x0d3f;
				break;
			}
			case 0x10:	/*PWM3-PWM2		BNA*/
			{
				if(dir==0)
				*ACTRA=0x0fd3;
				else
				*ACTRA=0x0f3d;
				break;
			}
			case 0x30:	/*PWM5-PWM2		CNA*/
			{
				if(dir==0)
				*ACTRA=0x0df3;
				else
				*ACTRA=0x03fd;
				break;
			}
			case 0x20:	/*PWM5-PWM4		CNB*/
			{
				if(dir==0)
				*ACTRA=0x0d3f;
				else
				*ACTRA=0x03df;
				break;
			}
			case 0x28:	/*PWM1-PWM4		ANB*/
			{
				if(dir==0)
				*ACTRA=0x0f3d;
				else
				*ACTRA=0x0fd3;
				break;
			}
			default:
			{
				*ACTRA=0x0fff;
			}
		}
		*CMPR3=*CMPR2=*CMPR1=PWM_DUTY;
		/*CMPR1=*CMPR2=*CMPR3=pwm_half_per/2;
		/*
		*CMPR1=(unsigned int)(pwm_half_per*(0.5+0.5*sin(((index_pwm)*2*PI)/(float)(num_f_d))));
		*CMPR2=(unsigned int)(pwm_half_per*(0.5+0.5*sin(((index_pwm+num_f_d/3)*2*PI)/(float)(num_f_d))));
		*CMPR3=(unsigned int)(pwm_half_per*(0.5+0.5*sin(((index_pwm+(num_f_d/3)*2)*2*PI)/(float)(num_f_d))));
		index_pwm++;
		if(index_pwm>300)index_pwm=1;
		*/ 
		
	} 
	/*asm(" CLRC INTM");*/
}