os_cpu.h

mips下的ucos

/* 
   Copyright (C) 2001, Lexra, Inc.
   Contributed by Pascal Cleve ([e-mail]).

   This code is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*/

#ifdef  OS_CPU_GLOBALS
#define OS_CPU_EXT
#else
#define OS_CPU_EXT  extern
#endif 

typedef unsigned char  BOOLEAN;
typedef unsigned char  INT8U;           /* Unsigned  8 bit quantity                           */
typedef signed   char  INT8S;           /* Signed    8 bit quantity                           */
typedef unsigned short INT16U;          /* Unsigned 16 bit quantity                           */
typedef signed   short INT16S;          /* Signed   16 bit quantity                           */
typedef unsigned long  INT32U;          /* Unsigned 32 bit quantity                           */
typedef signed   long  INT32S;          /* Signed   32 bit quantity                           */

typedef unsigned long  OS_STK;          /* Each stack entry is 32-bit wide                    */

#define BYTE           INT8S   		/* Define data types for backward compatibility ...   */
#define UBYTE          INT8U        	/* ... to uC/OS V1.xx.  Not actually needed for ...   */
#define WORD           INT16S           /* ... uC/OS-II.                                      */
#define UWORD          INT16U  
#define LONG           INT32S  
#define ULONG          INT32U  

typedef void (*FUNC)(void);

/* Status Register */
#define SR_CUMASK	0xf0000000	/* Coprocessor usable bits */
#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
#define SR_CU2		0x40000000	/* coprocessor 2 usable */
#define SR_CU1		0x20000000	/* Coprocessor 1 usable */
#define SR_CU0		0x10000000	/* Coprocessor 0 usable */
#define SR_BEV		0x00400000	/* Bootstrap Exception Vector */
#define SR_TS		0x00200000	/* TLB shutdown */
#define SR_PE		0x00100000	/* Parity Error */
#define SR_CM		0x00080000	/* Cache Miss */
#define SR_PZ		0x00040000	/* Parity Zero */
#define SR_SWC		0x00020000	/* Swap Caches */
#define SR_ISC		0x00010000	/* Isolate Cache */

#define SR_IMASK	0x0000ff00	/* Interrupt Mask */
#define SR_IMASK8	0x00000000	/* Interrupt Mask level=8 */
#define SR_IMASK7	0x00008000	/* Interrupt Mask level=7 */
#define SR_IMASK6	0x0000c000	/* Interrupt Mask level=6 */
#define SR_IMASK5	0x0000e000	/* Interrupt Mask level=5 */
#define SR_IMASK4	0x0000f000	/* Interrupt Mask level=4 */
#define SR_IMASK3	0x0000f800	/* Interrupt Mask level=3 */
#define SR_IMASK2	0x0000fc00	/* Interrupt Mask level=2 */
#define SR_IMASK1	0x0000fe00	/* Interrupt Mask level=1 */
#define SR_IMASK0	0x0000ff00	/* Interrupt Mask level=0 */

#define SR_IBIT8	0x00008000	/*  (Intr5) */
#define SR_IBIT7	0x00004000	/*  (Intr4) */
#define SR_IBIT6	0x00002000	/*  (Intr3) */
#define SR_IBIT5	0x00001000	/*  (Intr2) */
#define SR_IBIT4	0x00000800	/*  (Intr1) */
#define SR_IBIT3	0x00000400	/*  (Intr0) */
#define SR_IBIT2	0x00000200	/*  (Software Interrupt 1) */
#define SR_IBIT1	0x00000100	/*  (Software Interrupt 0) */
#define SR_INT5		0x00008000	/*  (Intr5) */
#define SR_INT4		0x00004000	/*  (Intr4) */
#define SR_INT3		0x00002000	/*  (Intr3) */
#define SR_INT2		0x00001000	/*  (Intr2) */
#define SR_INT1		0x00000800	/*  (Intr1) */
#define SR_INT0		0x00000400	/*  (Intr0) */

#define SR_KUO		0x00000020	/* Kernel/User mode, old */
#define SR_IEO		0x00000010	/* Interrupt Enable, old */
#define SR_KUP		0x00000008	/* Kernel/User mode, previous */
#define SR_IEP		0x00000004	/* Interrupt Enable, previous */
#define SR_KUC		0x00000002	/* Kernel/User mode, current */
#define SR_IEC		0x00000001	/* Interrupt Enable, current */

/* Cause Register */
#define CAUSE_BD		0x80000000	/* Branch Delay */
#define CAUSE_CEMASK		0x30000000	/* Coprocessor Error */
#define CAUSE_CESHIFT		28		/* Right justify CE  */
#define CAUSE_IPMASK		0x0000ff00	/* Interrupt Pending */
#define CAUSE_IPSHIFT		8		/* Right justify IP  */
#define CAUSE_IP8		0x00008000	/*  (Intr5) */
#define CAUSE_IP7		0x00004000	/*  (Intr4) */
#define CAUSE_IP6		0x00002000	/*  (Intr3) */
#define CAUSE_IP5		0x00001000	/*  (Intr2) */
#define CAUSE_IP4		0x00000800	/*  (Intr1) */
#define CAUSE_IP3		0x00000400	/*  (Intr0) */
#define CAUSE_INT5		0x00008000	/*  (Intr5) */
#define CAUSE_INT4		0x00004000	/*  (Intr4) */
#define CAUSE_INT3		0x00002000	/*  (Intr3) */
#define CAUSE_INT2		0x00001000	/*  (Intr2) */
#define CAUSE_INT1		0x00000800	/*  (Intr1) */
#define CAUSE_INT0		0x00000400	/*  (Intr0) */
#define CAUSE_SW2		0x00000200	/*  (Software Int 1) */
#define CAUSE_SW1		0x00000100	/*  (Software Int 0) */
#define CAUSE_EXCMASK		0x0000003c	/* Exception Code */
#define CAUSE_EXCSHIFT		2		/* Right justify EXC */

/* Exception Code */
#define EXC_INT		(0 << 2)	/* External interrupt */
#define EXC_MOD		(1 << 2)	/* TLB modification */
#define EXC_TLBL	(2 << 2)    	/* TLB miss (Load or Ifetch) */
#define EXC_TLBS	(3 << 2)	/* TLB miss (Save) */
#define EXC_ADEL	(4 << 2)    	/* Addr error (Load or Ifetch) */
#define EXC_ADES	(5 << 2)	/* Address error (Save) */
#define EXC_IBE		(6 << 2)	/* Bus error (Ifetch) */
#define EXC_DBE		(7 << 2)	/* Bus error (data load/store) */
#define EXC_SYS		(8 << 2)	/* System call */
#define EXC_BP		(9 << 2)	/* Break point */
#define EXC_RI		(10 << 2)	/* Reserved instruction */
#define EXC_CPU		(11 << 2)	/* Coprocessor unusable */
#define EXC_OVF		(12 << 2)	/* Arithmetic overflow */
#define EXC_TR          (13 << 2)       /* Trap instruction */

/* break instruction codes 0..1023 */
#define BRK_OVR		6		/* overflow */
#define BRK_DZERO	7		/* divide by zero */
#define BRK_TRAP	8		/* trap on condition */


#define OS_CRITICAL_METHOD 3
#define OS_ENTER_CRITICAL()  cpu_sr=disable_ints()	/* Disable interrupts  */
#define OS_EXIT_CRITICAL()   enable_ints(cpu_sr)  	/* Restore interrupts  */

/*
*********************************************************************************************************
*                           	Lexra Miscellaneous
*********************************************************************************************************
*/

#define  OS_STK_GROWTH        1                     /* Stack grows from HIGH to LOW memory  */

#define  OS_TASK_SW() OSCtxSw();


extern void    IRQDisable(int);
extern FUNC    IRQInstall(int, FUNC);

extern void BSPInit();