lconfig.form

mips下的ucos

JTAG_TRST_IS_TPC = "NO";


///////////////////////////////////////////////////////
//
// PC_TRACE -- EJTAG PC trace pins
//
// configuration choices:  NO EXPORT BUFFER
//
//         "NO"  --  EJTAG PC trace pins not added to lx2
//     "EXPORT"  --  EJTAG PC trace pins are added to lx2
//     "BUFFER"  --  Internal PC trace buffer is added
//
// The following settings are required when PC_TRACE = EXPORT:
//
//              JTAG = EXPORT or EXPORT_EXTENDED
//             EJTAG = YES
//
//
// The following settings are required when PC_TRACE = BUFFER:
//
//              JTAG = EXPORT or EXPORT_EXTENDED
//      EJTAG_DCLK_N = 1
//             EJTAG = YES
//
//
// This option provides EJTAG PC trace port on the lx2 module.
//
// default: PC_TRACE = "NO";
//
///////////////////////////////////////////////////////

PC_TRACE = "EXPORT";


///////////////////////////////////////////////////////
//
// PCTB_SEQ_WIDTH -- Number of bits in an internal PC trace buffer entry allocated to the seqential instruction count
//
// configuration choices:  <integer>
//
//    <integer>  --  number of bits (2 to 8)
//
// Number of bits in an internal PC trace buffer entry allocated to the
// sequential count field. This can range from 2 to 8 bits.
//
// default: PCTB_SEQ_WIDTH = 2;
//
///////////////////////////////////////////////////////

PCTB_SEQ_WIDTH = 2;


///////////////////////////////////////////////////////
//
// PCTB_STL_MAN_WIDTH -- Number of bits in an internal PC trace buffer entry allocated to the mantissa field of the stall count
//
// configuration choices:  0 <integer>
//
//          "0"  --  
//    <integer>  --  number of bits (0 to 4)
//
// The following settings are required when PCTB_STL_MAN_WIDTH = 0:
//
// PCTB_STL_EXP_WIDTH = 0
//
//
// Number of bits in an internal PC trace buffer entry allocated to the
// mantissa of the stall count field. This can range from 0 to 4 bits.
// When 0 is chosen the exponent part of the stall count must also set to
// 0 which results in the stall count field being removed from the PC
// trace buffer.
//
// default: PCTB_STL_MAN_WIDTH = 0;
//
///////////////////////////////////////////////////////

PCTB_STL_MAN_WIDTH = 0;


///////////////////////////////////////////////////////
//
// PCTB_STL_EXP_WIDTH -- Number of bits in an internal PC trace buffer entry allocated to the exponent field of the stall count
//
// configuration choices:  <integer>
//
//    <integer>  --  number of bits (0 to 4)
//
// Number of bits in an internal PC trace buffer entry allocated to the
// exponent of the stall count field. This can range from 0 to 4 bits.
// To remove the stall count field altogether, set both PCTB_STL_MAN_WIDTH and
// PCTB_STL_EXP_WIDTH lconfig options to 0.
//
// default: PCTB_STL_EXP_WIDTH = 0;
//
///////////////////////////////////////////////////////

PCTB_STL_EXP_WIDTH = 0;


///////////////////////////////////////////////////////
//
// PCTB_DEPTH -- Log base 2 of number of entries in internal PC trace buffer.
//
// configuration choices:  <integer>
//
//    <integer>  --  log base 2 number of buffer entries (2 or greater)
//
// Log base 2 the number of entries in internal PC trace buffer. 
// Valid options are 4 (16 entries) or greater. This is only
// instantiated if PC_TRACE="BUFFER".
//
// default: PCTB_DEPTH = 4;
//
///////////////////////////////////////////////////////

PCTB_DEPTH = 4;


///////////////////////////////////////////////////////
//
// EJTAG_DCLK_N -- EJTAG PCTrace DCLK N parameter
//
// configuration choices:  1 2 3 4 EXPORT
//
//          "1"  --  1-1 DCLK:SysClk period ratio.
//          "2"  --  2-1 DCLK:SysClk period ratio.
//          "3"  --  3-1 DCLK:SysClk period ratio.
//          "4"  --  4-1 DCLK:SysClk period ratio.
//     "EXPORT"  --  CFG_EJTNMINUS1 input port on LX module
//
// This is the integral ratio between the DCLK period and the
// processor core clock (SysClk) period.
// 
// If you choose EXPORT you must specify N-minus1 as a 2-bit value
// connected to the CFG_EJTNMINUS1 port of the lx2 module.
// 
// If you choose EXPORT and you are simulating with the evaulation
// board model (eb) supplied by Lexra (which would be the case if
// you select TESTBED_ENV = "EVAL_BOARD" or "TEST_CHIP" with this form),
// then you must provide a default setting for the jumper on the board.
// This is done with the CFGEXP_EJTNMINUS1 Verilog `define symbol.  For
// example, you can add any of the following statements to your lconfig
// form input file, which will produce the required `defines in
// lxr_symbols.vh:
// 
// 
//    SYMBOL `define CFGEXP_EJTNMINUS1 2'b00
// 
//              or
// 
//    SYMBOL `define CFGEXP_EJTNMINUS1 2'b01
// 
//    etc.
// 
// The correspondence between these values and the actual
// value of N is:
// 
//   CFGEXP_EJTNMINUS1   N
//   ----------          --- 
//    2'b00               1
//    2'b01               2
//    2'b10               3
//    2'b11               4
//
// default: EJTAG_DCLK_N = "2";
//
///////////////////////////////////////////////////////

EJTAG_DCLK_N = "EXPORT";


///////////////////////////////////////////////////////
//
// EJTAG_TPC_M -- EJTAG PCTrace TPC M parameter
//
// configuration choices:  1 2 4 8 EXPORT
//
//          "1"  --  1 TPC bit  per DCLK.
//          "2"  --  2 TPC bits per DCLK.
//          "4"  --  4 TPC bits per DCLK.
//          "8"  --  8 TPC bits per DCLK.
//     "EXPORT"  --  CFG_EJTMLOG2 input port on LX module
//
// This is the number of valid TPC bits driven during PCTracing
// at each DCLK.
// 
// If you choose EXPORT you must specify M-log2 as a 2-bit value
// connected to the CFG_EJTMLOG2 port of the lx2 module.
// 
// If you choose EXPORT and you are simulating with the evaulation
// board model (eb) supplied by Lexra (which would be the case if
// you select TESTBED_ENV = "EVAL_BOARD" or "TEST_CHIP" with this form),
// then you must provide a default setting for the jumper on the board.
// This is done with the CFGEXP_EJTMLOG2 Verilog `define symbol.  For
// example, you can add any of the following statements to your lconfig
// form input file, which will produce the required `defines in
// lxr_symbols.vh:
// 
//    SYMBOL `define CFGEXP_EJTMLOG2 2'b00
// 
//              or
// 
//    SYMBOL `define CFGEXP_EJTMLOG2 2'b01
// 
//    etc.
// 
// The correspondence between these values and the actual
// value of M is:
// 
//   CFGEXP_EJTMLOG2   M
//   --------          --- 
//    2'b00            1
//    2'b01            2
//    2'b10            4
//    2'b11            8
//
// default: EJTAG_TPC_M = "1";
//
///////////////////////////////////////////////////////

EJTAG_TPC_M = "EXPORT";


///////////////////////////////////////////////////////
//
// EJTAG_XV_BITS -- EJTAG PCTrace Number of Exception Vector bits
//
// configuration choices:  4 3 EXPORT
//
//          "4"  --  4-bit Exception Vector TPC output.
//          "3"  --  3-bit Exception Vector TPC output.
//     "EXPORT"  --  CFG_EJT3BITXVTPC input port on LX module
//
// This is the number of bits to be used for the EJTAG PCTrace
// Exception Vector driven serially on the TPC line(s) when the
// EXP code is output on the PCST lines.
// 
// If you use hardware low overhead vectored interrupts,
// then a 4-bit code (with the most significant bit set to 1)
// is used to indicate which one of the hardware interrupt vectors
// (numbered 8 through 15) has been taken when the EXP code is output.
// For other exceptions, the 4-bit code (with the most significant
// bit set to 0) has the standard value on its 3 least significant
// bits when the EXP code is output.
// 
// If your EJTAG probe vendor does not support this Lexra-specific
// extension to 4-bits, or if you do not use hardware vectored interrupts,
// you may use this parameter to disable the 4-bit code. In that case,
// only the standard 3-bit code is used when the EXP code is output.
// 
// (If the 4-bit code is disabled and a hardware vectored interrupt
// is taken, the NMI/Reset 3-bit code is used when the EXP code is output.)
// 
// If you choose EXPORT you must specify a 1-bit value
// connected to the CFG_EJT3BITXVTPC port of the lx2 module.
// 
// If you choose EXPORT and you are simulating with the evaulation
// board model (eb) supplied by Lexra (which would be the case if
// you select TESTBED_ENV = "EVAL_BOARD" or "TEST_CHIP" with this form),
// then you must provide a default setting for the jumper on the board.
// This is done with the CFGEXP_EJT3BITXVTPC Verilog `define symbol.  For
// example, you can add one of the following statements to your lconfig
// form input file, which will produce the required `defines in
// lxr_symbols.vh:
// 
//    SYMBOL `define CFGEXP_EJT3BITXVTPC 1'b0
// 
//              or
// 
//    SYMBOL `define CFGEXP_EJT3BITXVTPC 1'b1
// 
//    etc.
// 
// The correspondence between these values and the actual
// width of the Exception Vector is:
// 
//   EJT3BITXVTPC  XV-width
//   ------------  --------
//    1'b0           4-bits
//    1'b1           3-bits
//
// default: EJTAG_XV_BITS = "4";
//
///////////////////////////////////////////////////////

EJTAG_XV_BITS = "EXPORT";


///////////////////////////////////////////////////////
//
// EJTAG_PC_ISABIT -- EJTAG PCTrace Include ISA as PC Bit0
//
// configuration choices:  YES NO EXPORT
//
//        "YES"  --  32-bit PC for TPC output with ISA as Bit0.
//         "NO"  --  31-bit PC for TPC output.
//     "EXPORT"  --  CFG_EJTBIT0M16 input port on LX module
//
// This determines the number of bits to be used for the EJTAG PCTrace PC
// that is driven serially on the TPC line(s) when the JMP code is output
// on the PCST lines.
// 
// The EJTAG feature specifies that only a 31-bit PC (bits 31:1) should
// be output on the TPC line(s) by systems that are capable of executing
// code-compressed, 16-bit instructions (M16 ISA mode). (Systems that
// are not capable of executing in M16 mode use a 30-bit PC (bits 31:2)).
// 
// Some debug software that uses PCTrace information from an EJTAG
// probe can make good use of the ISA mode supplied as bit0 of the PC.
// 
// This parameter supports such debug software by enabling a 32-bit PC
// for systems which are M16 capable. For these systems, if this
// parameter is set to "YES", then bit0 is the first bit to be output on
// the TPC line(s) and has the value "1" if the target of the JMP-type
// instruction is in M16 ISA mode, and has the value "0" otherwise.
// (This usage of bit0 is consistent with its use in the EPC register and
// as the target of a JR instruction.)
// 
// Note: This parameter is ignored if the system is not capable of
// executing M16 mode instructions. In that case, a 30-bit PC (bits 31:2)
// is always used for output on the TPC line(s).
// 
// If you choose EXPORT you must specify a 1-bit value connected to the
// CFG_EJTBIT0M16 port of the lx2 module.
// 
// If you choose EXPORT and you are simulating with the evaulation board
// model (eb) supplied by Lexra (which would be the case if you select
// TESTBED_ENV = "EVAL_BOARD" or "TEST_CHIP" with this form), then you
// must provide a default setting for the jumper on the board.  This is
// done with the CFGEXP_EJTBIT0M16 Verilog `define symbol.  For example,
// you can add one of the following statements to your lconfig form input
// file, which will produce the required `defines in lxr_symbols.vh:
// 
//    SYMBOL `define CFGEXP_EJTBIT0M16 1'b0
// 
//              or
// 
//    SYMBOL `define CFGEXP_EJTBIT0M16 1'b1
// 
//    etc.
// 
// The correspondence between these values and the actual
// width of the output PC is:
// 
//   M16-capable?  PC-width (bits)  CFGEXP_EJTBIT0M16   
//   ------------  --------	 ----------   
//       no         30-bits (31:2)	 don't care   
//      yes         31-bits (31:1)	   1'b0       
//      yes         32-bits (31:0)	   1'b1       
//
// default: EJTAG_PC_ISABIT = "YES";
//
///////////////////////////////////////////////////////

EJTAG_PC_ISABIT = "EXPORT";


///////////////////////////////////////////////////////
//
// SCAN_INSERT -- Controls scan insertion and synthesis
//
// configuration choices:  YES NO
//
//        "YES"  --  Insert scan in the Lexra core and optional modules
//         "NO"  --  No Scan insertion will be performed
//
// The following s