lconfig.form

mips下的ucos

// default: DCACHE = "2K_1";
//
///////////////////////////////////////////////////////

DCACHE = "8K_1";


///////////////////////////////////////////////////////
//
// IMEM -- local instruction RAM
//
// configuration choices:  NONE RANGE
//
//                           "NONE"  --  not present
// RANGE (0xMMMM_LLL0, 0xMMMM_TTTf)  --  BASE and TOP values
//
// The decode logic for this LMI is configured with a base and top address
// range (inclusive).  The addressable region defined by this pair must be
// a power of 2 in size, from 1K bytes up to 256K bytes.  The region must
// be naturally aligned.  That is, a 1K byte region must be aligned at a
// modulo 1K byte address, a 2K byte region must be aligned at a modulo 2K
// byte address, etc.  The restrictions are imposed by the  LMI
// address decode logic to optimize for timing.
//  
// These address ranges are specified within the PHYSICAL address space.
// Keep in mind that the LX5280 transforms logical addresses to physical
// addresses before accessing local memory or sourcing transactions on the
// system bus. This translation affects the upper three bits of the address,
// and is shown here for convenience:
// 
//    LOGICAL      PHYSICAL        SEGMENT NAME
//     000           010           kuseg (cached)
//     001           011           kuseg (cached)
//     010           100           kuseg (cached)
//     011           101           kuseg (cached)
//     100           000           kseg0 (cached)
//     101           000           kseg1 (uncached)
//     110           110           kseg2 (cached)
//     111           111           kseg2 (cached)
// 
// Note that kseg0 and kseg1 map to the same physical address region.
// Also, the physical address region with the upper three bits = 001 is
// unreachable, i.e. there is no logical address that maps to that region.
// Example RANGE speficiations:
// 
//     RANGE (0x4004_1000, 0x4004_17ff)
//     RANGE (0xa000_0000, 0xa000_03ff)
//
// default: IMEM = "NONE";
//
///////////////////////////////////////////////////////

//IMEM = RANGE (0x4040_0000, 0x4040_1fff);
IMEM = "NONE";

///////////////////////////////////////////////////////
//
// IROM -- local instruction ROM
//
// configuration choices:  NONE RANGE
//
//                           "NONE"  --  not present
// RANGE (0xMMMM_LLL0, 0xMMMM_TTTf)  --  BASE and TOP values
//
// The following settings are required when IROM = RANGE:
//
//       IMEM_IS_ROM = NO
//
//
// See the IRAM section above for details on setting the range bounds.
//
// default: IROM = "NONE";
//
///////////////////////////////////////////////////////

IROM = "NONE";


///////////////////////////////////////////////////////
//
// IMEM_IS_ROM -- declare local instruction RAM is actually ROM
//
// configuration choices:  NO YES
//
//         "NO"  --  IMEM, if present, is truly a RAM
//        "YES"  --  IMEM, if present, is actually a ROM
//
// This is an obsolete option that is supported for backward compatibility only.
// For new applications that require ROM, IMEM_IS_ROM should be set to NO,
// and IROM = RANGE (<base>, <top>) should be specified.  See section above.
// 
// The rest of this documentation describes IMEM_IS_ROM for backward
// compatible appplications.
// 
// When IMEM is present, it normally responds only to cacheable references.
// The IMEM will not respond to any Kseg1 references.  This behavior is
// ensured by setting IMEM_IS_ROM = "NO".
// 
// Alternatively, IMEM may be configured as a ROM controller by setting
// IMEM_IS_ROM = "YES".  This setting allows the IMEM controller to respond
// to Kseg1 (uncacheable) address, and should be used if you wish to
// execute boot code (starting at physical address 1fc0_0000) in the ROM.
// Choosing this setting will cause the IMEM instruction store to be
// instanced in the lx2 layer.
//
// default: IMEM_IS_ROM = "NO";
//
///////////////////////////////////////////////////////

IMEM_IS_ROM = "NO";


///////////////////////////////////////////////////////
//
// DMEM -- local scratch pad data RAM
//
// configuration choices:  NONE RANGE
//
//                           "NONE"  --  not present
// RANGE (0xMMMM_LLL0, 0xMMMM_TTTf)  --  BASE and TOP values
//
// See the IMEM section above for details on setting the range bounds.
//
// default: DMEM = "NONE";
//
///////////////////////////////////////////////////////

DMEM = RANGE (0x4051_0000, 0x4051_1fff);


///////////////////////////////////////////////////////
//
// LMI_DATA_GRANULARITY -- DCACHE and DMEM write granularity
//
// configuration choices:  WORD BYTE
//
//       "WORD"  --  DCACHE and DMEM have word write granularity
//       "BYTE"  --  DCACHE and DMEM have byte write granularity
//
// The following settings are required when LMI_DATA_GRANULARITY = BYTE:
//
//   MEM_GRANULARITY = BYTE
//
//
// This setting determines the DCACHE and DMEM write granularity.  See
// the MEM_GRANULARITY option to specify system memory write granularity.
// 
// Selecting BYTE for this option allows store byte and store half-word
// instructions that hit the DCACHE or DMEM to complete in one cycle.  In
// this case the application specific SRAMs that are used must provide
// a byte write capability.
// 
// If the SRAMs do not provide a byte-write capability, you must select WORD
// for this option.  All byte and half-word stores that hit the DCACHE or
// DMEM will result in read-modify-write operations to DMEM, which require
// two cycle to complete.
//
// default: LMI_DATA_GRANULARITY = "WORD";
//
///////////////////////////////////////////////////////

LMI_DATA_GRANULARITY = "WORD";


///////////////////////////////////////////////////////
//
// LMI_RANGE_SOURCE -- source of LMI address ranges
//
// configuration choices:  HARDWIRED EXPORT
//
//  "HARDWIRED"  --  hardwired values derived from configuration RANGE values
//     "EXPORT"  --  inputs to LX module
//
// Selecting HARDWIRED will force the LMI address ranges to those entered above
// under IMEM and DMEM 'RANGE' settings.  Otherwise, selecting EXPORT will enable
// application specific logic to drive configuration values onto IWC_BASE[31:16],
// IWC_TOP[15:4], DWC_BASE[31:16], and DWC_TOP[15:4] to specify the above
// settings.  See the description for IMEM and DMEM, and the LX5280 data sheet 
// for additional information.
//
// default: LMI_RANGE_SOURCE = "HARDWIRED";
//
///////////////////////////////////////////////////////

LMI_RANGE_SOURCE = "EXPORT";


///////////////////////////////////////////////////////
//
// LMI_RAM_ARB -- allow external agents to arbitrate for LMI RAMs
//
// configuration choices:  NO YES
//
//         "NO"  --  do not provide arbitration for LMI RAMs
//        "YES"  --  provide arbitration for LMI RAMs
//
// Selecting YES allows external agents to request access to the RAMs that
// that are normally controlled by the LX5280 LMIs.  Each LMI supplies
// a request line input and grant line output.  When a given LMI's request
// input is asserted, the LMI will assert its grant line to the external
// agent when it is safe to allow the agent to access the RAMs.  The LMI
// will inhibit its own accesses to the RAMs until the external request
// line is de-asserted.
// 
// The request/grant lines are ports on the lx2 module, and are present
// only if LMI_RAM_ARB is set to YES and the corresponding LMI is populated.
// An input in the list below is an input to the LX5280, at the lx2 module
// level.  An output is an output from the lx2 module level.
// 
//   input  EXT_IWREQRAM_R; // external agent drives 1'b1 to request IMEM
//   output IW_GNTRAM_R;    // IMEM LMI drives 1'b1 to grant external agent
// 
//   input  EXT_DWREQRAM_R; // external agent drives 1'b1 to request DMEM
//   output DW_GNTRAM_R;    // DMEM LMI drives 1'b1 to grant external agent
// 
//   input  EXT_ICREQRAM_R; // external agent drives 1'b1 to request ICACHE
//   output IC_GNTRAM_R;    // ICACHE LMI drives 1'b1 to grant external agent
// 
//   input  EXT_DCREQRAM_R; // external agent drives 1'b1 to request DCACHE
//   output DC_GNTRAM_R;    // DCACHE LMI drives 1'b1 to grant external agent
//
// default: LMI_RAM_ARB = "NO";
//
///////////////////////////////////////////////////////

LMI_RAM_ARB = "NO";


///////////////////////////////////////////////////////
//
// JTAG -- Internal JTAG Tap controller with EJTAG support
//
// configuration choices:  NO EXPORT EXPORT_EXTENDED
//
//         "NO"  --  EJTAG support is NOT added
//     "EXPORT"  --  JTAG tap is added, tap wires exported to outside of lx2
// "EXPORT_EXTENDED"  --  JTAG tap IS added, tap wires and additional state signals exported to outside of chip
//
// This option controls instancing of the internal JTAG Tap controller.
// 
// Select "EXPORT" if you wish to use the Lexra supplied TAP controller with
// EJTAG, and you do not require additional scan chains.  The TAP ports will
// be exported from the lx2 layer.
// 
// Select "EXPORT_EXTENDED" to instance the TAP conroller in lx1 and export
// additional scan chain ports that you can connect to your own scan chains.
// The standard TAP ports and additional chains will be exported from the
// lx2 layer.
// 
// Select "NO" if you do not wish to use Lexra's TAP controller.  If you
// you choose NO and your configuration includes EJTAG, then the EJTAG
// scan chain ports will be exported from the lx2 layer, and you must
// connect them to your own TAP controller.
//
// default: JTAG = "NO";
//
///////////////////////////////////////////////////////

JTAG = "EXPORT";


///////////////////////////////////////////////////////
//
// EJTAG -- EJTAG Debug Support
//
// configuration choices:  NO YES
//
//         "NO"  --  EJTAG support is NOT added
//        "YES"  --  EJTAG support IS added
//
// The following settings are required when EJTAG = YES:
//
//              JTAG = EXPORT or EXPORT_EXTENDED
//
//
// This includes the EJTAG Debug Support hardware, including breakpoint support
// of the instruction, data, and Lexra busses, as well as the PC Trace facility, EJTAG DMA
// facility, and EJTAG interrupts.  You must select YES if configuring any breakpoint
// support.  (See the next three options.)  If you select YES but do not specify
// breakpoint support, the resulting configuration will support PC Trace,
// EJTAG DMA and EJTAG interrupts.  Selecting NO removes all support for these items.
//
// default: EJTAG = "NO";
//
///////////////////////////////////////////////////////

EJTAG = "YES";


///////////////////////////////////////////////////////
//
// EJTAG_INST_BREAK -- Number of instruction breaks to be compiled
//
// configuration choices:  <integer>
//
//    <integer>  --  number of instruction breaks (0 to 15)
//
// This is the number of EJTAG instruction breakpoints to be compiled.
// If the number of breakpoints is non-zero, the ejtag_imatch module
// will be instanced in the chip module.
//
// default: EJTAG_INST_BREAK = 0;
//
///////////////////////////////////////////////////////

EJTAG_INST_BREAK = 4;


///////////////////////////////////////////////////////
//
// EJTAG_DATA_BREAK -- Number of data breaks to be compiled
//
// configuration choices:  <integer>
//
//    <integer>  --  number of data breaks (0 to 15)
//
// This is the number of EJTAG data breakpoints to be compiled.
// If the number of breakpoints is non-zero, the ejtag_dmatch module
// will be instanced in the chip module.
//
// default: EJTAG_DATA_BREAK = 0;
//
///////////////////////////////////////////////////////

EJTAG_DATA_BREAK = 2;


///////////////////////////////////////////////////////
//
// JTAG_TRST_IS_TPC -- TRST pin is used as TPC out to eliminate TDO/TPC mux
//
// configuration choices:  YES NO
//
//        "YES"  --  TRST input replaced by TPC output
//         "NO"  --  TDI/DINT and TDO/TPC are muxed as in the EJTAG spec
//
// The following settings are required when JTAG_TRST_IS_TPC = YES:
//
//       TESTBED_ENV = CHIP or DEVBOARD
//
//
// Normally, when PCRACE is enabled, the meaning of the TDI and TDO pins change 
// to DINT and TPC.  On a multiprocessor system with multiple TAP controllers
// cascaded, if one CPU goes into PCTRACE modes, the scan chain is broken. 
// Furthemore, any attempt to scan will likely generate an unwanted DINT.
// 
// When this option is "YES", TPC becomes a seperate output signal to the
// probe.  Since there  are no extra pins available, TRST is sacrificed.  This
// is generally ok since the TAP controller can be reset with five consecutive
// TMS=1.  The loss of DINT is easily worked around since DINT is also
// a scable control bit.
// 
// A side advantage to this is that the TPC signal is no longer multiplexed and
// the skew between it and other TPC bits (if any) becomes zero.
// 
// This option should be turned on when there are multiple CPUs and/or when
// a compatible probe is going to be connected.
// 
// NOTE: IF THIS OPTION IS TURNED ON AND A NON-EPI-MODIFIED PROBE IS USED,
// THERE MAY BE CONFLICTING SIGNALS ON THE PROBE CONNECTOR (TPC and TRST).
// 
// Turn this off if a non-EPI probe or older EPI probe is being used.  Off is
// the EJTAG "standard" selection.
//
// default: JTAG_TRST_IS_TPC = "NO";
//
///////////////////////////////////////////////////////