lconfig.form

mips下的ucos

// board.  This is done with the CFGEXP_MEMSEQUENTIAL Verilog `define symbol.  For
// example, you can add any of the following statements to your lconfig
// form input file, which will produce the required `define in
// lxr_symbols.vh:
// 
//    SYMBOL `define CFGEXP_MEMSEQUENTIAL 1'b0  // INTERLEAVE
// 
//              or
// 
//    SYMBOL `define CFGEXP_MEMSEQUENTIAL 1'b1  // SEQUENTIAL
//
// default: MEM_LINE_ORDER = "SEQUENTIAL";
//
///////////////////////////////////////////////////////

MEM_LINE_ORDER = "EXPORT";


///////////////////////////////////////////////////////
//
// MEM_FIRST_WORD -- cache line fill first word
//
// configuration choices:  DESIRED ZERO EXPORT
//
//    "DESIRED"  --  desired word first
//       "ZERO"  --  word 0 first
//     "EXPORT"  --  external logic drives CFG_MEMZEROFIRST port of LX module
//
// This setting declares the line read first word policy of the
// user's main memory implementation, and configures the LX5280
// to correctly work with that policy.
// 
// You must configure the LX5280 to match the first word policy of your
// main memory controller.  This ensures that the LX5280 performs a line
// read from memory that the words will be stored in the correct offsets
// within the cache line.
// 
// The first two choices result in hardwired setting of this attribute.
// The third choice allows application specific logic to drive a
// configuration value onto the CFG_MEMZEROFIRST port of lx2.v to specify
// the attribute setting.  Sourcing a logic one on the wire results
// in the ZERO mode of operation, and sourcing a logic zero on the
// wire results in the DESIRED mode of operation.
// 
// If you choose EXPORT and you are simulating with the evaulation
// board model (eb) supplied by Lexra (which would be the case if
// you select TESTBED_ENV = "EVAL_BOARD" or "TEST_CHIP" with this form),
// then you must also provide a default setting for the jumper on the
// board.  This is done with the CFGEXP_MEMZEROFIRST Verilog `define symbol.  For
// example, you can add any of the following statements to your lconfig
// form input file, which will produce the required `define in
// lxr_symbols.vh:
// 
//    SYMBOL `define CFGEXP_MEMZEROFIRST 1'b0  // DESIRED
// 
//              or
// 
//    SYMBOL `define CFGEXP_MEMZEROFIRST 1'b1  // ZERO
//
// default: MEM_FIRST_WORD = "DESIRED";
//
///////////////////////////////////////////////////////

MEM_FIRST_WORD = "EXPORT";


///////////////////////////////////////////////////////
//
// MEM_GRANULARITY -- main memory system partial word write support
//
// configuration choices:  WORD BYTE EXPORT
//
//       "WORD"  --  main memory has word granularity
//       "BYTE"  --  main memory has byte granularity
//     "EXPORT"  --  external logic drives CFG_MEMFULLWORD port of LX module
//
// This setting declares the write granularity of the
// user's main memory implementation, and configures the LX5280
// to correctly work with that policy.
// 
// This setting declares the main memory write granularity.  See the
// LMI_DATA_GRANULARITY option to specify DCACHE and DMEM write granularity.
// 
// If main memory supports byte writes, selecting BYTE for this option
// allows store byte and store half-word instructions to complete
// without requiring the affected memory word to be resident in the
// data cache.
// 
// If main memory does not support byte writes, you must select WORD
// for this option, and all byte and half-word stores will allocate
// a line in the data cache if the data is not already resident.  This
// is necessary for the cache to construct a full word of data to
// write to main memory.
// 
// The first two choices result in hardwired setting of this attribute.
// The third choice allows application specific logic to drive a
// configuration value onto the CFG_MEMFULLWORD port of lx2.v to specify
// the attribute setting.  Sourcing a logic one on the wire results
// in the WORD mode of operation, and sourcing a logic zero on the
// wire results in the BYTE mode of operation.
// 
// If you choose EXPORT and you are simulating with the evaulation
// board model (eb) supplied by Lexra (which would be the case if
// you select TESTBED_ENV = "EVAL_BOARD" or "TEST_CHIP" with this form),
// then you must also provide a default setting for the jumper on the
// board.  This is done with the CFGEXP_MEMFULLWORD Verilog `define symbol.  For
// example, you can add any of the following statements to your lconfig
// form input file, which will produce the required `define in
// lxr_symbols.vh:
// 
//    SYMBOL `define CFGEXP_MEMFULLWORD 1'b0  // BYTE
// 
//              or
// 
//    SYMBOL `define CFGEXP_MEMFULLWORD 1'b1  // WORD
//
// default: MEM_GRANULARITY = "WORD";
//
///////////////////////////////////////////////////////

MEM_GRANULARITY = "EXPORT";


///////////////////////////////////////////////////////
//
// SYSTEM_INTERFACE -- system bus interface type
//
// configuration choices:  LBUS CBUS
//
//       "LBUS"  --  Lexra system bus with Lexra bus controller
//       "CBUS"  --  Lexra cache bus with processor bus interface
//
// The following settings are required when SYSTEM_INTERFACE = CBUS:
//
//      PRODUCT_TYPE = RTL or PLD
//     LBC_SYNC_MODE = SYNCHRONOUS
//
//
// The Lexra processor can either connect to the system through the
// standard Lexra bus or through a customer defined bus interface.
// If the Lexra bus is selected then the Lexra bus master controller
// (LBC) will be instanciated.  If the cache bus is selected then
// an external interface must be designed to connect to the Lexra
// cache bus.
//
// default: SYSTEM_INTERFACE = "LBUS";
//
///////////////////////////////////////////////////////

SYSTEM_INTERFACE = "LBUS";


///////////////////////////////////////////////////////
//
// LBC_WBUF -- Lexra Bus Controller write buffer depth
//
// configuration choices:  <integer>
//
//    <integer>  --  number of write buffer entries (2 to 16)
//
// Adding more write buffers could improve system performance
// at a cost of additional real estate.  16 write buffers may
// improve performance by as much as 5 percent over 4 buffers.
// The minimum setting is 2.  Each write buffer adds about 67
// flip flops and compare logic for 33 bits.
//
// default: LBC_WBUF = 4;
//
///////////////////////////////////////////////////////

LBC_WBUF = 4;


///////////////////////////////////////////////////////
//
// LBC_RBUF -- Lexra Bus Controller read buffer depth
//
// configuration choices:  <integer>
//
//    <integer>  --  number of read buffer entries (2 to 2*line size)
//
// Typically, the number of read buffer entries should be 8.  This is enough
// to hold two 4-word lines of read data which are needed if there are
// simultaneous I-cache and D-cache misses.  The read buffer allows the system
// memory to transfer lines as fast as possible without having to wait for cache
// to absorb the data.  The read buffer will never overflow when set to 8
// (two lines).
// 
// However, to save area, the number of entries can be reduced with some cost to
// bus utilization.  If the read buffer fills while memory is trying to send
// read data, the LBC will deassert IRDY until it can accept more data, thus
// reducing bus utilization.  By reducing the number of entries to 4, the buffer
// will still be able to accomodate one full line, so IRDY would be deasserted
// only in the relatively infrequent case where there are simultaneous I-cache
// and D-cache misses.  By reducing the depth to 2 -- the minimum -- area is
// optimized in favor of bus utilization.
// 
// Note: 2 read buffer entries are all that are needed for a synchronous LBC.
//
// default: LBC_RBUF = 8;
//
///////////////////////////////////////////////////////

LBC_RBUF = "8";


///////////////////////////////////////////////////////
//
// LBC_RDBYPASS -- Lexra Bus Controller read bypass enable
//
// configuration choices:  YES NO EXPORT
//
//        "YES"  --  enable read bypass of LBC write buffer
//         "NO"  --  disable read bypass of LBC write buffer
//     "EXPORT"  --  external logic drives CFG_LBCWBDISABLE port of LX module
//
// The LBC's write buffer normally allows read operations presented
// by the processor to bypass write operations that are pending
// in the write buffer.  If the line address of a read operation
// matches the line address of any writes pending in the write
// buffer, the LBC will stall the read until the writes
// are completed.  This type of operation is achieved by
// setting LBC_RDBYPASS to YES.
// 
// The read bypass acceleration can be disabled by setting
// LBC_RDBYPASS to NO.  This will cause all reads presented
// to the LBC to wait for the write buffer empty.
// 
// The first two choices result in hardwired setting of bypass control.
// The third choice allows application specific logic to drive a
// configuration value onto the CFG_LBCWBDISABLE port of lx2.v 
// to specify the attribute setting.  Sourcing a logic one on
// the wire results in read bypass being disabled, and sourcing a
// logic zero on the wire results in read bypass being enabled.
// 
// If you choose EXPORT and you are simulating with the evaulation
// board model (eb) supplied by Lexra (which would be the case if
// you select TESTBED_ENV = "EVAL_BOARD" or "TEST_CHIP" with this form),
// then you must also provide a default setting for the jumper on the
// board.  This is done with the CFGEXP_LBCWBDISABLE Verilog `define
// symbol.  For example, you can add any of the following statements to
// your lconfig form input file, which will produce the required
// `defines in lxr_symbols.vh:
// 
//    SYMBOL `define CFGEXP_LBCWBDISABLE 1'b0 // ENABLED
// 
//              or
// 
//    SYMBOL `define CFGEXP_LBCWBDISABLE 1'b1 // DISABLED
// 
//
// default: LBC_RDBYPASS = "YES";
//
///////////////////////////////////////////////////////

LBC_RDBYPASS = "EXPORT";


///////////////////////////////////////////////////////
//
// LBC_SYNC_MODE -- LBC synchronous/asynchronous selection
//
// configuration choices:  SYNCHRONOUS ASYNCHRONOUS
//
// "SYNCHRONOUS"  --  Same clock used for SysClk and BusClk
// "ASYNCHRONOUS"  --  Different clock used for SysClk and BusClk
//
// By default, the LBC is asynchronous and allows the SysClk and the
// BusClk to be driven from two independent clock generators.  The
// BusClk frequency can be anywhere between DC and twice the frequency
// of the SysClk.  If the SysClk and the BusClk will be generated from
// the same source, select "SYNCHRONOUS" mode.  This will cause the
// asynchronous interface to be bypassed and will greatly reduce the
// latency caused by the asynchronous interface.
//
// default: LBC_SYNC_MODE = "ASYNCHRONOUS";
//
///////////////////////////////////////////////////////

LBC_SYNC_MODE = "ASYNCHRONOUS";


///////////////////////////////////////////////////////
//
// LINE_SIZE -- cache line size, in words
//
// configuration choices:  4 8 16 32
//
//          "4"  --  line size is 4 words
//          "8"  --  line size is 8 words
//         "16"  --  line size is 16 words
//         "32"  --  line size is 32 words
//
// The following settings are required when LINE_SIZE = 8:
//
//      PRODUCT_TYPE = RTL or PLD
//
//
// The following settings are required when LINE_SIZE = 16:
//
//      PRODUCT_TYPE = RTL or PLD
//
//
// The following settings are required when LINE_SIZE = 32:
//
//      PRODUCT_TYPE = RTL or PLD
//
//
// This setting declares the line size, in words, of the ICACHE, DCACHE,
// IMEM and LBC.  Your memory system must supply this number of words in
// reponse to a system bus line read command.
//
// default: LINE_SIZE = "4";
//
///////////////////////////////////////////////////////

LINE_SIZE = "4";


///////////////////////////////////////////////////////
//
// ICACHE -- instruction cache size
//
// configuration choices:  NONE 64K_2 32K_2 16K_2 8K_2 4K_2 2K_2 1K_2 64K_1 32K_1 16K_1 8K_1 4K_1 2K_1 1K_1
//
//       "NONE"  --  no instruction cache
//      "64K_2"  --  64K byte 2-way set associative instruction cache
//      "32K_2"  --  32K byte 2-way set associative instruction cache
//      "16K_2"  --  16K byte 2-way set associative instruction cache
//       "8K_2"  --  8K byte 2-way set associative instruction cache
//       "4K_2"  --  4K byte 2-way set associative instruction cache
//       "2K_2"  --  2K byte 2-way set associative instruction cache
//       "1K_2"  --  1K byte 2-way set associative instruction cache
//      "64K_1"  --  64K byte direct mapped instruction cache
//      "32K_1"  --  32K byte direct mapped instruction cache
//      "16K_1"  --  16K byte direct mapped instruction cache
//       "8K_1"  --  8K byte direct mapped instruction cache
//       "4K_1"  --  4K byte direct mapped instruction cache
//       "2K_1"  --  2K byte direct mapped instruction cache
//       "1K_1"  --  1K byte direct mapped instruction cache
//
// default: ICACHE = "2K_1";
//
///////////////////////////////////////////////////////

ICACHE = "8K_1";


///////////////////////////////////////////////////////
//
// DCACHE -- data cache size
//
// configuration choices:  NONE 64K_1 32K_1 16K_1 8K_1 4K_1 2K_1 1K_1
//
//       "NONE"  --  no data cache
//      "64K_1"  --  64K byte direct mapped data cache
//      "32K_1"  --  32K byte direct mapped data cache
//      "16K_1"  --  16K byte direct mapped data cache
//       "8K_1"  --  8K byte direct mapped data cache
//       "4K_1"  --  4K byte direct mapped data cache
//       "2K_1"  --  2K byte direct mapped data cache
//       "1K_1"  --  1K byte direct mapped data cache
//
// The following settings are required when DCACHE = NONE:
//
//   MEM_GRANULARITY = BYTE
//
//