lconfig.form

mips下的ucos

// The following settings are required when SEN_BUFFERS = EXTERNAL:
//
//       SCAN_INSERT = YES
//
//
// 
//
// default: SEN_BUFFERS = "NONE";
//
///////////////////////////////////////////////////////

SEN_BUFFERS = "NONE";


///////////////////////////////////////////////////////
//
// SLEEP -- include clock SLEEP support
//
// configuration choices:  YES NO EXPORT
//
//        "YES"  --  include clock SLEEP support
//         "NO"  --  do not include clock SLEEP support
//     "EXPORT"  --  clock SLEEP support, with CFG_SLEEP_ENABLE pin
//
// An optional sleep mode can be accessed via software or hardware if
// enabled via this option.  The LX5280 uses clock gating to implement
// its sleep mode.  Users who do not allow clock gating should select
// "NO" for option, and will not have access to the LX5280 sleep mode.
// 
// Sleep mode is implemented in the lx2/lx1/lx0/reset_dist module,
// when enabled by this setting, and can be accessed via software or
// hardware as described in the LX5280 data sheet.
// 
// The clock gating for sleep mode is implemented in the clock buffers.
// For the LX5280 RTL product, these buffers reside either inside or
// outside the lx2 module, as determined by the CLOCK_BUFFERS setting
// below.  When sleep is enabled, clock sleep terms are sourced by
// the reset_dist module and received by the clock buffers for gating
// with the free running input clock.
// 
// If you choose EXPORT and you are simulating with the evaulation
// board model (eb) supplied by Lexra (which would be the case if
// you select TESTBED_ENV = "EVAL_BOARD" or "TEST_CHIP" with this form),
// then you must also provide a default setting for the jumper on the
// board.  This is done with the CFGEXP_SLEEPENABLE Verilog `define
// symbol.  For  example, you can add any of the following statements to
// your lconfig form input file, which will produce the required
// `defines in lxr_symbols.vh:
// 
//    SYMBOL `define CFGEXP_SLEEPENABLE 1'b0 // DISABLED
// 
//              or
// 
//    SYMBOL `define CFGEXP_SLEEPENABLE 1'b1 // ENABLED
// 
//
// default: SLEEP = "NO";
//
///////////////////////////////////////////////////////

SLEEP = "EXPORT";


///////////////////////////////////////////////////////
//
// RESET_BUFFERS -- Reset buffers at the lx2 module level
//
// configuration choices:  EXTERNAL LX2
//
//   "EXTERNAL"  --  user supplies external reset buffers
//        "LX2"  --  include reset buffers in the lx2 module
//
// This setting controls the method used to buffer resets used in the LX5280
// hierarchy.
// 
// Choosing LX2 will cause buffers to be instanced in the lx2 module.
// Each reset brought into the lx2 module will be passed through an 
// lx2 buffer, and the buffered copy is passed down throughout the 
// hierarchy.
// 
// Choosing EXTERNAL will export each reset brought into the lx2 module.
// You may then connect your own buffers to these outputs.
//
// default: RESET_BUFFERS = "EXTERNAL";
//
///////////////////////////////////////////////////////

RESET_BUFFERS = "EXTERNAL";


///////////////////////////////////////////////////////
//
// CLOCK_BUFFERS -- clock buffers at lx2 module level
//
// configuration choices:  EXTERNAL LX2
//
//   "EXTERNAL"  --  user supplies external clock buffers
//        "LX2"  --  include clock buffers in lx2 module
//
// This setting controls the method used to buffer clocks used in the LX5280
// hiearchy.  
// 
// Choosing LX2 will cause buffers to be instanced in the lx2.
// Each clock brought into the lx2 module will be passed through an lx2 
// buffer, and the buffered copy is passed as pure wire througout the
// hierarchy.  This option should be used for physical design flows that
// can turn the input buffer and clock wires into a balanced clock tree
// distributed throughout the lx2/lx1/lx0 module hiearchy.  If LX2
// is chosen for this option, lconfig will select generic buffer
// modules for RTL simulation, and identify them to allow users to
// define technology specific versions.
// 
// Choosing EXTERNAL will cause pure wires to be used for clock connections
// throughout the lx2/lx1/lx0 hierarchy.  This option should be chosen
// if the user's ASIC flow cannot properly interpret the clock buffers
// on the lx2 inputs, or if the user desires to handle tree synthesis
// and layout at higher level than lx2.
// 
// Note that for Lexra products that support sleep, if sleep mode is enabled
// (SLEEP="YES"), then the clock buffers for SYSCLK (and optionally BUSCLK)
// will include clock sleep terms sourced by the sleep logic.
// 
// For RAM clock tuning, the user can also use RAM clock buffers instanced
// within each LMI that controls RAMs.  See RAM_CLOCK_BUFFERS below.
//
// default: CLOCK_BUFFERS = "EXTERNAL";
//
///////////////////////////////////////////////////////

CLOCK_BUFFERS = "EXTERNAL";


///////////////////////////////////////////////////////
//
// RAM_CLOCK_BUFFERS -- LMI RAM clock distribution method
//
// configuration choices:  YES NO
//
//        "YES"  --  compile RAM clock buffers into LMI modules
//         "NO"  --  use system level clock for RAMs
//
// This option determines how clocks are distributed to the RAMs
// attached to the LMI controllers.  Select YES to drive the output
// of the local clock buffer in each LMI to the clock inputs
// of the RAMs attached to each LMI.  This method should be
// should be used if the application uses a hierarchical clock
// tree as specified in  the LX5280 layout guidelines.
// Select NO to drive the system wide clock directly to the RAMs.
// This method should be used if the application employs its
// own clock distribution method.
//
// default: RAM_CLOCK_BUFFERS = "NO";
//
///////////////////////////////////////////////////////

RAM_CLOCK_BUFFERS = "NO";


///////////////////////////////////////////////////////
//
// COP1 -- coprocessor interface 1
//
// configuration choices:  NONE COPSTUB CUSTOM EXPORT
//
//       "NONE"  --  coprocessor 1 not exported from the core
//    "COPSTUB"  --  coprocessor 1 interface connected to a test model in the Lexra testbed.
//     "CUSTOM"  --  coprocessor 1 interface connected to customer logic to be simulated in the Lexra testbed.
//     "EXPORT"  --  coprocessor 1 interface connected to customer logic but not simulated in the Lexra testbed.
//
// This option determines whether the coprocessor 1 interface is
// exported and how it is treated by the Lexra testbed.
// 
// NONE, the coprocessor interface will not be exported from the
// core.
//   
// COPSTUB, the coprocessor interface will be exported from the
// core and connected to a coprocessor model in the Lexra testbed
// for regression testing.  This option may be used for initial
// verification of the core, but should not be used for the
// customer's final design.
//   
// CUSTOM, the coprocessor interface will be exported from the core
// and the customer will connect their coprocessor model to the
// core and run simulations with the Lexra testbed.
//   
// EXPORT, the coprocessor interface will be exported from the core
// but no coprocessor simulation model will be used in Lexra's
// testbed.
//
// default: COP1 = "NONE";
//
///////////////////////////////////////////////////////

COP1 = "NONE";


///////////////////////////////////////////////////////
//
// COP2 -- coprocessor interface 2
//
// configuration choices:  NONE COPSTUB CUSTOM EXPORT
//
//       "NONE"  --  coprocessor 2 not exported from the core
//    "COPSTUB"  --  coprocessor 2 interface connected to a test model in the Lexra testbed.
//     "CUSTOM"  --  coprocessor 2 interface connected to customer logic to be simulated in the Lexra testbed.
//     "EXPORT"  --  coprocessor 2 interface connected to customer logic but not simulated in the Lexra testbed.
//
// This option determines whether the coprocessor 2 interface is
// exported and how it is treated by the Lexra testbed.
// 
// NONE, the coprocessor interface will not be exported from the
// core.
//   
// COPSTUB, the coprocessor interface will be exported from the
// core and connected to a coprocessor model in the Lexra testbed
// for regression testing.  This option may be used for initial
// verification of the core, but should not be used for the
// customer's final design.
//   
// CUSTOM, the coprocessor interface will be exported from the core
// and the customer will connect their coprocessor model to the
// core and run simulations with the Lexra testbed.
//   
// EXPORT, the coprocessor interface will be exported from the core
// but no coprocessor simulation model will be used in Lexra's
// testbed.
//
// default: COP2 = "NONE";
//
///////////////////////////////////////////////////////

COP2 = "EXPORT";


///////////////////////////////////////////////////////
//
// COP3 -- coprocessor interface 3
//
// configuration choices:  NONE COPSTUB CUSTOM EXPORT
//
//       "NONE"  --  coprocessor 3 not exported from the core
//    "COPSTUB"  --  coprocessor 3 interface connected to a test model in the Lexra testbed.
//     "CUSTOM"  --  coprocessor 3 interface connected to customer logic to be simulated in the Lexra testbed.
//     "EXPORT"  --  coprocessor 3 interface connected to customer logic but not simulated in the Lexra testbed.
//
// This option determines whether the coprocessor 3 interface is
// exported and how it is treated by the Lexra testbed.
// 
// NONE, the coprocessor interface will not be exported from the
// core.
//   
// COPSTUB, the coprocessor interface will be exported from the
// core and connected to a coprocessor model in the Lexra testbed
// for regression testing.  This option may be used for initial
// verification of the core, but should not be used for the
// customer's final design.
//   
// CUSTOM, the coprocessor interface will be exported from the core
// and the customer will connect their coprocessor model to the
// core and run simulations with the Lexra testbed.
//   
// EXPORT, the coprocessor interface will be exported from the core
// but no coprocessor simulation model will be used in Lexra's
// testbed.
//
// default: COP3 = "NONE";
//
///////////////////////////////////////////////////////

COP3 = "COPTC3";


///////////////////////////////////////////////////////
//
// CE0 -- custom engine 0
//
// configuration choices:  NONE CE_MAC CE_MACD CE_HL
//
//       "NONE"  --  custom engine 0 not present
//     "CE_MAC"  --  Lexra mul/div/MAC module
//    "CE_MACD"  --  Lexra Dual mul/div/MAC module
//      "CE_HL"  --  Lexra MFHI/MFLO/MTHI/MTLO module
//
// default: CE0 = "CE_MACD";
//
///////////////////////////////////////////////////////

CE0 = "CE_MACD";


///////////////////////////////////////////////////////
//
// CE1 -- custom engine 1
//
// configuration choices:  NONE CE_DVT EXPORT
//
//       "NONE"  --  custom engine 1 not present
//     "CE_DVT"  --  Lexra simulation testbed custom engine
//     "EXPORT"  --  export CE1 interface from LX module
//
// The following settings are required when CE1 = NONE:
//
//               CE0 = CE_MAC, CE_MACD or CE_HL
//
//
// default: CE1 = "NONE";
//
///////////////////////////////////////////////////////

CE1 = "EXPORT";


///////////////////////////////////////////////////////
//
// M16_SUPPORT -- 16-bit opcode support
//
// configuration choices:  YES NO
//
//        "YES"  --  enable decode and execution of 16-bit opcodes
//         "NO"  --  disable decode and execution of 16-bit opcodes
//
// M16 code compression can be used to improve code density for systems in
// which on-chip instruction storage is a premium.  In some configurations and
// technologies M16 support may have a negative effect on the system clock rate.
// A small amount of die area is consumed by M16 so for applications that have
// no need for code compression it is best to disable M16 support.
//
// default: M16_SUPPORT = "YES";
//
///////////////////////////////////////////////////////

M16_SUPPORT = "YES";
CHIP_PORT_INCLUDE = "YES";
CHIP_INOUT_INCLUDE = "YES";
CHIP_WIRE_INCLUDE = "YES";
CHIP_INSTANCE_INCLUDE = "YES";


///////////////////////////////////////////////////////
//
// MEM_LINE_ORDER -- cache line fill beat ordering
//
// configuration choices:  INTERLEAVE SEQUENTIAL EXPORT
//
// "INTERLEAVE"  --  interleave ordering, low bit toggles
// "SEQUENTIAL"  --  increment ordering, wrap to zero
//     "EXPORT"  --  external logic drives CFG_MEMSEQUENTIAL port of LX module
//
// This setting declares the line read word ordering policy of the
// user's main memory implementation, and configures the LX5280
// to correctly work with that policy.
// 
// You must configure the LX5280 to match the line order policy of your
// main memory controller.  This ensures that the LX5280 performs a line
// read from memory that the words will be stored in the correct offsets
// within the cache line.
// 
// The first two choices result in hardwired setting of this attribute.
// The third choice allows application specific logic to drive a
// configuration value onto the CFG_MEMSEQUENTIAL port of lx2.v to specify
// the attribute setting.  Sourcing a logic one on the wire results
// in the SEQUENTIAL mode of operation, and sourcing a logic zero on the
// wire results in the INTERLEAVE mode of operation.
// 
// If you choose EXPORT and you are simulating with the evaulation
// board model (eb) supplied by Lexra (which would be the case if
// you select TESTBED_ENV = "EVAL_BOARD" or "TEST_CHIP" with this form),
// then you must also provide a default setting for the jumper on the