lconfig.form

mips下的ucos

// lconfig configuration form for LX5280
// 
// Copyright 1997-2001, Lexra Inc.
// ALL RIGHTS RESERVED
// 
// == user/lx5280_tc.form; version 1.45; swdemo release ZL224 ==
// 
// This form is processed by the lconfig tool to configure the
// LX5280 RTL source code for user specific options.  To
// configure the RTL source code, edit this form to indicate the
// desired options, and execute the lconfig utility within the
// include directory.
// 
// A starting form with properly configured default values can be
// obtained with the command
// 
//   "lconfig -blank_form <output_filename>"
// 
// To configure the RTL, review each of the sections in the new form
// and fill in the desired values based on your application
// requirements.  Then process the form with the lconfig tool.
// The tool will produce the symbol file (lxr_symbols.vh) that is
// used for RTL simulation and also by the synthesis process.
// lconfig also produces a configuration dependent tests list,
// lxr_tests.vh, this is used by the regesssion script to test
// the RTL configuration in the Lexra supplied simulation testbed.
// 
// DO NOT EDIT THE RESULTING LXR_SYMBOLS.VH FILE BY HAND.
// 
// A summary of the configurable elements appears below.  Following
// this summary are the detailed sections for each configurable
// element.
//
//            PRODUCT -- Lexra Processor
//       PRODUCT_TYPE -- indicates product type
//       REGFILE_TECH -- 
//         TECHNOLOGY -- identifies target technology
//        TESTBED_ENV -- identifies simulation testbed environment type
//         RESET_TYPE -- flip-flop reset method
//         RESET_DIST -- reset distribution method
//           SEN_DIST -- Scan Enable Distribution Method
//        SEN_BUFFERS -- Scan Enable Buffering at lx2
//              SLEEP -- include clock SLEEP support
//      RESET_BUFFERS -- Reset buffers at the lx2 module level
//      CLOCK_BUFFERS -- clock buffers at lx2 module level
//  RAM_CLOCK_BUFFERS -- LMI RAM clock distribution method
//               COP1 -- coprocessor interface 1
//               COP2 -- coprocessor interface 2
//               COP3 -- coprocessor interface 3
//                CE0 -- custom engine 0
//                CE1 -- custom engine 1
//        M16_SUPPORT -- 16-bit opcode support
//     MEM_LINE_ORDER -- cache line fill beat ordering
//     MEM_FIRST_WORD -- cache line fill first word
//    MEM_GRANULARITY -- main memory system partial word write support
//   SYSTEM_INTERFACE -- system bus interface type
//           LBC_WBUF -- Lexra Bus Controller write buffer depth
//           LBC_RBUF -- Lexra Bus Controller read buffer depth
//       LBC_RDBYPASS -- Lexra Bus Controller read bypass enable
//      LBC_SYNC_MODE -- LBC synchronous/asynchronous selection
//          LINE_SIZE -- cache line size, in words
//             ICACHE -- instruction cache size
//             DCACHE -- data cache size
//               IMEM -- local instruction RAM
//               IROM -- local instruction ROM
//        IMEM_IS_ROM -- declare local instruction RAM is actually ROM
//               DMEM -- local scratch pad data RAM
// LMI_DATA_GRANULARITY -- DCACHE and DMEM write granularity
//   LMI_RANGE_SOURCE -- source of LMI address ranges
//        LMI_RAM_ARB -- allow external agents to arbitrate for LMI RAMs
//               JTAG -- Internal JTAG Tap controller with EJTAG support
//              EJTAG -- EJTAG Debug Support
//   EJTAG_INST_BREAK -- Number of instruction breaks to be compiled
//   EJTAG_DATA_BREAK -- Number of data breaks to be compiled
//   JTAG_TRST_IS_TPC -- TRST pin is used as TPC out to eliminate TDO/TPC mux
//           PC_TRACE -- EJTAG PC trace pins
//     PCTB_SEQ_WIDTH -- Number of bits in an internal PC trace buffer entry allocated to the seqential instruction count
// PCTB_STL_MAN_WIDTH -- Number of bits in an internal PC trace buffer entry allocated to the mantissa field of the stall count
// PCTB_STL_EXP_WIDTH -- Number of bits in an internal PC trace buffer entry allocated to the exponent field of the stall count
//         PCTB_DEPTH -- Log base 2 of number of entries in internal PC trace buffer.
//       EJTAG_DCLK_N -- EJTAG PCTrace DCLK N parameter
//        EJTAG_TPC_M -- EJTAG PCTrace TPC M parameter
//      EJTAG_XV_BITS -- EJTAG PCTrace Number of Exception Vector bits
//    EJTAG_PC_ISABIT -- EJTAG PCTrace Include ISA as PC Bit0
//        SCAN_INSERT -- Controls scan insertion and synthesis
//    SCAN_MIX_CLOCKS -- Scan Chains can cross clock boundaries with lock-up latches
//    SCAN_NUM_CHAINS -- Number of scan chains in LX1
//           SCAN_SCL -- A Scan collar will be inserted on RAM interfaces
//       RAM_BIST_MUX -- include test RAM mux and ports on lx2 module



///////////////////////////////////////////////////////
//
// PRODUCT -- Lexra Processor
//
// configuration choices:  LX4189 LX4280 LX5180 LX5280 LX8000
//
//     "LX4189"  --  LX4189 Processor
//     "LX4280"  --  LX4280 Processor
//     "LX5180"  --  LX5180 Processor
//     "LX5280"  --  LX5280 Processor
//     "LX8000"  --  LX8000 Processor
//
// The following settings are required when PRODUCT = LX4189:
//
//               CE0 = CE_MAC, CE_HL or NONE
//
//
// The following settings are required when PRODUCT = LX4280:
//
//      EJTAG_DCLK_N = 2, 4 or EXPORT
//               CE0 = CE_MAC, CE_HL or NONE
//
//
// The following settings are required when PRODUCT = LX5180:
//
//               CE0 = CE_MACD
//
//
// The following settings are required when PRODUCT = LX5280:
//
//      EJTAG_DCLK_N = 2, 4 or EXPORT
//               CE0 = CE_MACD
//
//
// The following settings are required when PRODUCT = LX8000:
//
//       M16_SUPPORT = NO
//               CE0 = CE_HL or NONE
//             SLEEP = NO
//
//
// default: PRODUCT = "LX5280";
//
///////////////////////////////////////////////////////

PRODUCT = "LX5280";


///////////////////////////////////////////////////////
//
// PRODUCT_TYPE -- indicates product type
//
// configuration choices:  RTL PLD
//
//        "RTL"  --  RTL source product
//        "PLD"  --  Programmable Logic Device implementation
//
// The following settings are required when PRODUCT_TYPE = RTL:
//
//       SCAN_INSERT = YES or NO
//
//
// The following settings are required when PRODUCT_TYPE = PLD:
//
//        TECHNOLOGY = CUSTOM
//        RESET_TYPE = ASYNCHRONOUS
//        RESET_DIST = GLOBAL
// RAM_CLOCK_BUFFERS = NO
//             SLEEP = NO
//       SCAN_INSERT = NO
//      RAM_BIST_MUX = NO
//
//
// default: PRODUCT_TYPE = "RTL";
//
///////////////////////////////////////////////////////

PRODUCT_TYPE = "RTL";
CUSTOM_FILES = "YES";


///////////////////////////////////////////////////////
//
// REGFILE_TECH -- 
//
// configuration choices:  RAM FLOP
//
//        "RAM"  --  Regfile implemented in RAM (or similar vendor provided core)
//       "FLOP"  --  Regfile synthesized from standard cells
//
// The following settings are required when REGFILE_TECH = RAM:
//
//           PRODUCT = LX8000
//
//
// If an appropriate RAM or regfile core exists for a chosen target technology,
// it may be used to implement the register file of the CPU.  Otherwise the
// regfile will be synthesized from standard flip-flop cells.
// 
// A RAM based regfile is typically slower than a flop based regfile, and may
// affect the critical path in the CPU.  Scan can not be used to test a RAM, and
// some ASIC libraries do not offer a 4-port (2 read, 2 write) RAM, which is
// required to implement the regfile.
// 
// A RAM based regfile typically requires less area to layout than a flop based
// implementation.  This benefits large configurations such as hardware multi-
// context or multi-processor designs.
//
// default: REGFILE_TECH = "FLOP";
//
///////////////////////////////////////////////////////

REGFILE_TECH = "FLOP";


///////////////////////////////////////////////////////
//
// TECHNOLOGY -- identifies target technology
//
// configuration choices:  CUSTOM
//
//     "CUSTOM"  --  customer defined technology (any name beginning with CUSTOM)
//
// You may define custom technologies by choosing a technology name that begins
// with the string "CUSTOM", and consisting of all uppercase characters,
// numbers and an underscore.  Within the LX5280 project directory,
// sub-directories with this same name, but in lowercase form, can then be used
// to hold custom versions of the RTL files as needed.
//
// default: TECHNOLOGY = "CUSTOM";
//
///////////////////////////////////////////////////////

TECHNOLOGY = "ARTISAN_TSMC18";


///////////////////////////////////////////////////////
//
// TESTBED_ENV -- identifies simulation testbed environment type
//
// configuration choices:  CHIP DEVBOARD
//
//       "CHIP"  --  minimum chip level simulation environment
//   "DEVBOARD"  --  Lexra development board environment
//
// The following settings are required when TESTBED_ENV = CHIP:
//
//              COP3 = NONE, COPSTUB, CUSTOM or EXPORT
//
//
// The following settings are required when TESTBED_ENV = DEVBOARD:
//
//               CE1 = NONE or EXPORT
//              COP1 = NONE, CUSTOM or EXPORT
//              COP2 = NONE, CUSTOM or EXPORT
//              COP3 = NONE, CUSTOM or EXPORT
//
//
// Lexra supplies a Verilog simulation environment for this release
// of the LX5280.  You must select CHIP for this option.
// 
// The chip level environment is a minimal simulation testbench for
// a configurable LX5280 chip design, with a simple memory
// responder attached to the Lexra processor.  This provides you
// with a working simulation environment that can grow with your
// design.
// 
//
// default: TESTBED_ENV = "CHIP";
//
///////////////////////////////////////////////////////

TESTBED_ENV = "TEST_CHIP";


///////////////////////////////////////////////////////
//
// RESET_TYPE -- flip-flop reset method
//
// configuration choices:  SYNCHRONOUS ASYNCHRONOUS
//
// "SYNCHRONOUS"  --  use synchronous resetable flip-flops
// "ASYNCHRONOUS"  --  use asynchronous resetable flip-flops
//
// default: RESET_TYPE = "SYNCHRONOUS";
//
///////////////////////////////////////////////////////

RESET_TYPE = "SYNCHRONOUS";


///////////////////////////////////////////////////////
//
// RESET_DIST -- reset distribution method
//
// configuration choices:  LOCAL_SAMPLED LOCAL_BUFFERED GLOBAL
//
// "LOCAL_SAMPLED"  --  distribute reset from local flip-flops
// "LOCAL_BUFFERED"  --  distribute reset from local buffers
//     "GLOBAL"  --  distribute reset from global driver
//
// The RESET_DIST option determines how the signals are distributed
// from lx2/lx1/lx0/reset_dist module.  Because reset signals are
// high fanout, they may require special treatment in some ASIC
// flows, which this setting accomodates.
// 
// Choose GLOBAL if your ASIC design flow will completely handle
// buffering and fanout of reset signals.  This setting results
// in pure wires and port connections being used throughout
// the LX5280 heirarchy.
// 
// Choose LOCAL_BUFFERED to insert buffers in each major LX5280
// module.  This provides buffering throughout the hierarchy,
// and may be practical for most applications.
// 
// Choose LOCAL_SAMPLED to insert a flop that samples reset coming
// into each major LX5280 module, which is then distributed within
// the module.  This provides purely local timing requirements for reset
// within each module, and is easier to achieve than LOCAL_BUFFERED.
//
// default: RESET_DIST = "LOCAL_SAMPLED";
//
///////////////////////////////////////////////////////

RESET_DIST = "LOCAL_SAMPLED";


///////////////////////////////////////////////////////
//
// SEN_DIST -- Scan Enable Distribution Method
//
// configuration choices:  GLOBAL LOCAL_BUFFERED NONE
//
//     "GLOBAL"  --  Global Scan Enable Distribution
// "LOCAL_BUFFERED"  --  Locally Buffered Scan Enable Distribution
//       "NONE"  --  Do Not Distribute Scan Enable
//
// The following settings are required when SEN_DIST = GLOBAL:
//
//       SCAN_INSERT = YES
//
//
// The following settings are required when SEN_DIST = LOCAL_BUFFERED:
//
//       SCAN_INSERT = YES
//
//
// The following settings are required when SEN_DIST = NONE:
//
//       SCAN_INSERT = NO
//
//
// 
//
// default: SEN_DIST = "NONE";
//
///////////////////////////////////////////////////////

SEN_DIST = "NONE";


///////////////////////////////////////////////////////
//
// SEN_BUFFERS -- Scan Enable Buffering at lx2
//
// configuration choices:  LX2 EXTERNAL NONE
//
//        "LX2"  --  Buffer Scan Enable at lx2
//   "EXTERNAL"  --  Buffer Scan Enable outside of lx2
//       "NONE"  --  Do Not Buffer Scan Enable
//
// The following settings are required when SEN_BUFFERS = LX2:
//
//       SCAN_INSERT = YES
//
//