int.h

LCD driver 程序

#define		INT_E8TU1		0x02		// 8bit timer1 underflow interrupt enable
#define		INT_E8TU0		0x01		// 8bit timer0 underflow interrupt enable
#define		INT_ESTX1		0x20		// Serial interface ch.1 transmit buffer empty interrupt enable
#define		INT_ESRX1		0x10		// Serial interface ch.1 receive buffer full interrupt enable
#define		INT_ESERR1		0x08		// Serial interface ch.1 receive error interrupt enable
#define		INT_ESTX0		0x04		// Serial interface ch.0 transmit buffer empty interrupt enable
#define		INT_ESRX0		0x02		// Serial interface ch.0 receive buffer full interrupt enable
#define		INT_ESERR0		0x01		// Serial interface ch.0 receive error interrupt enable
#define		INT_EP7			0x20		// Input port7 interrupt enable
#define		INT_EP6			0x10		// Input port6 interrupt enable
#define		INT_EP5			0x08		// Input port5 interrupt enable
#define		INT_EP4			0x04		// Input port4 interrupt enable
#define		INT_ECTM		0x02		// Clock timer interrupt enable
#define		INT_EADE		0x01		// A/D converter convert end interrupt enable
#define		INT_ENABLE_DIS		0x00		// interrupt enable register all bit disable

#define		INT_FK1			0x20		// Key input1 interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FK0			0x10		// Key input0 interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FP3			0x08		// Input port3 interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FP2			0x04		// Input port2 interupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FP1			0x02		// Input port1 interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FP0			0x01		// Input port0 interrupt ractor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FIDMA		0x10		// IDMA interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FHSDMA3		0x08		// HSDMA ch3 interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FHSDMA2		0x04		// HSDMA ch2 interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FHSDMA1		0x02		// HSDMA ch1 interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FHSDMA0		0x01		// HSDMA ch0 interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F16TC1		0x80		// 16bit timer1 comparison match A interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F16TU1		0x40		// 16bit timer1 comparsion match B interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F16TC0		0x08		// 16bit timer0 comparison match A interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F16TU0		0x04		// 16bit timer0 comparison match B interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F16TC3		0x80		// 16bit timer3 comparison match A interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F16TU3		0x40		// 16bit timer3 comparison match B interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F16TC2		0x08		// 16bit timer2 comparison match A interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F16TU2		0x04		// 16bit timer2 comparison match B interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F16TC5		0x80		// 16bit timer5 comparison match A interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F16TU5		0x40		// 16bit timer5 comparison match B interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F16TC4		0x08		// 16bit timer4 comparison match A interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F16TU4		0x04		// 16bit timer4 comparison match B interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F8TU3		0x08		// 8bit timer3 underflow interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F8TU2		0x04		// 8bit timer2 underflow interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F8TU1		0x02		// 8bit timer1 underflow interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_F8TU0		0x01		// 8bit timer0 underflow interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FSTX1		0x20		// Serial interface ch.1 transmit buffer empty interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FSRX1		0x10		// Serial interface ch.1 receive buffer full interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FSERR1		0x08		// Serial interface ch.1 receive error interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FSTX0		0x04		// Serial interface ch.0 transmit buffer empty interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FSRX0		0x02		// Serial interface ch.0 receive buffer full interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FSERR0		0x01		// Serial interface ch.0 receive error interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FP7			0x20		// Input port7 interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FP6			0x10		// Input port6 interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FP5			0x08		// Input port5 interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FP4			0x04		// Input port4 interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FCTM		0x02		// Clock timer interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FADE		0x01		// A/D converter convert end interrupt factor is reset in read only mode, interrupt factor is generated in read/write mode
#define		INT_FLAG_RST		0xff		// Interrupt factor flag all reset (interrupt factor flag read only mode)

#define		INT_R16TC0		0x80		// 16bit timer0 comparison match IDMA request
#define		INT_R16TU0		0x40		// 16bit timer0 underflow IDMA request
#define		INT_RHDM1		0x20		// HSDMA DMA ch.1 IDMA request
#define		INT_RHDM0		0x10		// HSDMA DMA ch.0 IDMA request
#define		INT_RP3			0x08		// Input port3 IDMA request
#define		INT_RP2			0x04		// Input port2 IDMA request
#define		INT_RP1			0x02		// Input port1 IDMA request
#define		INT_RP0			0x01		// Input port0 IDMA request
#define		INT_R16TC4		0x08		// 16bit timer4 comparison match A IDMA request
#define		INT_R16TU4		0x04		// 16bit timer4 comparsion match B IDMA request
#define		INT_R16TC3		0x02		// 16bit timer3 comparison match A IDMA request
#define		INT_R16TU3		0x01		// 16bit timer3 comparsion match B IDMA request
#define		INT_R16TC2		0x08		// 16bit timer2 comparison match A IDMA request
#define		INT_R16TU2		0x04		// 16bit timer2 comparsion match B IDMA request
#define		INT_R16TC1		0x02		// 16bit timer1 comparison match A IDMA request
#define		INT_R16TU1		0x01		// 16bit timer1 comparsion match B IDMA request
#define		INT_RSTX0		0x80		// Serial interface ch.0 transmit DBF IDMA request
#define		INT_RSRX0		0x40		// Serial interface ch.0 receive DBF IDMA request
#define		INT_R8TU3		0x20		// 8bit timer3 underflow IDMA request
#define		INT_R8TU2		0x10		// 8bit timer2 underflow IDMA request
#define		INT_R8TU1		0x08		// 8bit timer1 underflow IDMA request
#define		INT_R8TU0		0x04		// 8bit timer0 underflow IDMA request
#define		INT_R16TC5		0x02		// 16bit timer5 comparison match A IDMA request
#define		INT_R16TU5		0x01		// 16bit timer5 comparison match B IDMA request
#define		INT_RP7			0x80		// Input port7 IDMA request
#define		INT_RP6			0x40		// Input port6 IDMA request
#define		INT_RP5			0x20		// Input port5 IDMA request
#define		INT_RP4			0x10		// Input port5 IDMA request
#define		INT_RADE		0x04		// A/D converter convert end IDMA request
#define		INT_RSTX1		0x02		// Serial interface ch.1 transmit buffer empty IDMA request
#define		INT_RSRX1		0x01		// Serial interface ch.1 receive buffer full IDMA request
#define		INT_RIDMA_DIS		0x00		// IDMA request is all disable and CPU request is all enable

#define		INT_DENONLY_RST		0x04		// IDMA enable register set read only mode
#define		INT_DENONLY_RDWR	0x00		// IDMA enable register set read/write mode

#define		INT_IDMAONLY_RST	0x02		// IDMA request register set read only mode
#define		INT_IDMAONLY_RDWR	0x00		// IDMA request register set read/write mode

#define		INT_RSTONLY_RST		0x01		// Interrupt factor flag reset read only mode
#define		INT_RSTONLY_RDWR	0x00		// Interrupt factor flag reset read/write mode