atm128_sim.h

tinyos-2.x.rar

#ifndef ATM128_SIM_H_INCLUDED
#define ATM128_SIM_H_INCLUDED

/*
 * In normal avr code, the address and identifier of a register can be
 * the same. In a parallel simulation, this runs into issues with C typing,
 * as there are actually many copies of a register. So in TOSSIM the standard
 * name (e.g., PINE) refers to the actual memory location of the register while
 * ATM128_ (e.g., ATM128_PINE) refers to the register identifier.
 *
 */

//uint8_t atm128RegFile[100][0xa0];

#define _BV(bit) (1 << (bit))
//#define __SFR_OFFSET 0x20

#define _MMIO_BYTE(mem_addr) (*((volatile uint8_t *)(&atm128RegFile[sim_node()][mem_addr])))
#define _MMIO_WORD(mem_addr) (*((volatile uint16_t *)(&atm128RegFile[sim_node()][mem_addr])))
#define _SFR_MEM8(mem_addr) _MMIO_BYTE(mem_addr)
#define _SFR_MEM16(mem_addr) _MMIO_WORD(mem_addr)
#define _SFR_IO8(io_addr) _MMIO_BYTE((io_addr) )
#define _SFR_IO16(io_addr) _MMIO_WORD((io_addr) )

enum {
/* Input Pins, Port F */
  ATM128_PINF    = 0x00,

/* Input Pins, Port E */
  ATM128_PINE    = 0x01,

/* Data Direction Register, Port E */
  ATM128_DDRE    = 0x02,

/* Data Register, Port E */
  ATM128_PORTE   = 0x03,

/* ADC Data Register */
  ATM128_ADCW    = 0x04, /* for backwards compatibility */
#ifndef __ASSEMBLER__
  ATM128_ADC     = 0x04,
#endif
  ATM128_ADCL    = 0x04,
  ATM128_ADCH    = 0x05,

/* ADC Control and status register */
  ATM128_ADCSR   = 0x06,
  ATM128_ADCSRA  = 0x06, /* new name in datasheet (2467E-AVR-05/02) */

/* ADC Multiplexer select */
  ATM128_ADMUX   = 0x07,

/* Analog Comparator Control and Status Register */
  ATM128_ACSR    = 0x08,

/* USART0 Baud Rate Register Low */
  ATM128_UBRR0L  = 0x09,

/* USART0 Control and Status Register B */
  ATM128_UCSR0B  = 0x0A,

/* USART0 Control and Status Register A */
  ATM128_UCSR0A  = 0x0B,

/* USART0 I/O Data Register */
  ATM128_UDR0    = 0x0C,

/* SPI Control Register */
  ATM128_SPCR    = 0x0D,

/* SPI Status Register */
  ATM128_SPSR    = 0x0E,

/* SPI I/O Data Register */
  ATM128_SPDR    = 0x0F,

/* Input Pins, Port D */
  ATM128_PIND    = 0x10,

/* Data Direction Register, Port D */
  ATM128_DDRD    = 0x11,

/* Data Register, Port D */
  ATM128_PORTD   = 0x12,

/* Input Pins, Port C */
  ATM128_PINC    = 0x13,

/* Data Direction Register, Port C */
  ATM128_DDRC    = 0x14,

/* Data Register, Port C */
  ATM128_PORTC   = 0x15,

/* Input Pins, Port B */
  ATM128_PINB    = 0x16,

/* Data Direction Register, Port B */
  ATM128_DDRB    = 0x17,

/* Data Register, Port B */
  ATM128_PORTB   = 0x18,

/* Input Pins, Port A */
  ATM128_PINA    = 0x19,

/* Data Direction Register, Port A */
  ATM128_DDRA    = 0x1A,

/* Data Register, Port A */
  ATM128_PORTA   = 0x1B,

/* 0x1C..0x1F EEPROM */

/* Special Function I/O Register */
  ATM128_SFIOR   = 0x20,

/* Watchdog Timer Control Register */
  ATM128_WDTCR   = 0x21,

/* On-chip Debug Register */
  ATM128_OCDR    = 0x22,

/* Timer2 Output Compare Register */
  ATM128_OCR2    = 0x23,

/* Timer/Counter 2 */
  ATM128_TCNT2   = 0x24,

/* Timer/Counter 2 Control register */
  ATM128_TCCR2   = 0x25,

/* T/C 1 Input Capture Register */
  ATM128_ICR1    = 0x26,
  ATM128_ICR1L   = 0x26,
  ATM128_ICR1H   = 0x27,

/* Timer/Counter1 Output Compare Register B */
  ATM128_OCR1B   = 0x28,
  ATM128_OCR1BL  = 0x28,
  ATM128_OCR1BH  = 0x29,

/* Timer/Counter1 Output Compare Register A */
  ATM128_OCR1A   = 0x2A,
  ATM128_OCR1AL  = 0x2A,
  ATM128_OCR1AH  = 0x2B,

/* Timer/Counter 1 */
  ATM128_TCNT1   = 0x2C,
  ATM128_TCNT1L  = 0x2C,
  ATM128_TCNT1H  = 0x2D,

/* Timer/Counter 1 Control and Status Register */
  ATM128_TCCR1B  = 0x2E,

/* Timer/Counter 1 Control Register */
  ATM128_TCCR1A  = 0x2F,

/* Timer/Counter 0 Asynchronous Control & Status Register */
  ATM128_ASSR    = 0x30,

/* Output Compare Register 0 */
  ATM128_OCR0    = 0x31,

/* Timer/Counter 0 */
  ATM128_TCNT0   = 0x32,

/* Timer/Counter 0 Control Register */
  ATM128_TCCR0   = 0x33,

/* MCU Status Register */
  ATM128_MCUSR   = 0x34,
  ATM128_MCUCSR  = 0x34, /* new name in datasheet (2467E-AVR-05/02) */

/* MCU general Control Register */
  ATM128_MCUCR   = 0x35,

/* Timer/Counter Interrupt Flag Register */
  ATM128_TIFR    = 0x36,

/* Timer/Counter Interrupt MaSK register */
  ATM128_TIMSK   = 0x37,

/* External Interrupt Flag Register */
  ATM128_EIFR    = 0x38,

/* External Interrupt MaSK register */
  ATM128_EIMSK   = 0x39,

/* External Interrupt Control Register B */
  ATM128_EICRB   = 0x3A,

/* RAM Page Z select register */
  ATM128_RAMPZ   = 0x3B,

/* XDIV Divide control register */
  ATM128_XDIV    = 0x3C,

/* 0x3D..0x3E SP */

/* 0x3F SREG */
  ATM128_SREG    = 0x3F,

/* Extended I/O registers */

/* Data Direction Register, Port F */
  ATM128_DDRF    = 0x61,

/* Data Register, Port F */
  ATM128_PORTF   = 0x62,

/* Input Pins, Port G */
  ATM128_PING    = 0x63,

/* Data Direction Register, Port G */
  ATM128_DDRG    = 0x64,

/* Data Register, Port G */
  ATM128_PORTG   = 0x65,

/* Store Program Memory Control and Status Register */
  ATM128_SPMCR   = 0x68,
  ATM128_SPMCSR  = 0x68, /* new name in datasheet (2467E-AVR-05/02) */

/* External Interrupt Control Register A */
  ATM128_EICRA   = 0x6A,

/* External Memory Control Register B */
  ATM128_XMCRB   = 0x6C,

/* External Memory Control Register A */
  ATM128_XMCRA   = 0x6D,

/* Oscillator Calibration Register */
  ATM128_OSCCAL  = 0x6F,

/* 2-wire Serial Interface Bit Rate Register */
  ATM128_TWBR    = 0x70,

/* 2-wire Serial Interface Status Register */
  ATM128_TWSR    = 0x71,

/* 2-wire Serial Interface Address Register */
  ATM128_TWAR    = 0x72,

/* 2-wire Serial Interface Data Register */
  ATM128_TWDR    = 0x73,

/* 2-wire Serial Interface Control Register */
  ATM128_TWCR    = 0x74,

/* Time Counter 1 Output Compare Register C */
  ATM128_OCR1C   = 0x78,
  ATM128_OCR1CL  = 0x78,
  ATM128_OCR1CH  = 0x79,

/* Timer/Counter 1 Control Register C */
  ATM128_TCCR1C  = 0x7A,

/* Extended Timer Interrupt Flag Register */
  ATM128_ETIFR   = 0x7C,

/* Extended Timer Interrupt Mask Register */
  ATM128_ETIMSK  = 0x7D,

/* Timer/Counter 3 Input Capture Register */
  ATM128_ICR3    = 0x80,
  ATM128_ICR3L   = 0x80,
  ATM128_ICR3H   = 0x81,

/* Timer/Counter 3 Output Compare Register C */
  ATM128_OCR3C   = 0x82,
  ATM128_OCR3CL  = 0x82,
  ATM128_OCR3CH  = 0x83,

/* Timer/Counter 3 Output Compare Register B */
  ATM128_OCR3B   = 0x84,
  ATM128_OCR3BL  = 0x84,
  ATM128_OCR3BH  = 0x85,

/* Timer/Counter 3 Output Compare Register A */
  ATM128_OCR3A   = 0x86,
  ATM128_OCR3AL  = 0x86,
  ATM128_OCR3AH  = 0x87,

/* Timer/Counter 3 Counter Register */
  ATM128_TCNT3   = 0x88,
  ATM128_TCNT3L  = 0x88,
  ATM128_TCNT3H  = 0x89,

/* Timer/Counter 3 Control Register B */
  ATM128_TCCR3B  = 0x8A,

/* Timer/Counter 3 Control Register A */
  ATM128_TCCR3A  = 0x8B,

/* Timer/Counter 3 Control Register C */
  ATM128_TCCR3C  = 0x8C,

/* USART0 Baud Rate Register High */
  ATM128_UBRR0H  = 0x90,

/* USART0 Control and Status Register C */
  ATM128_UCSR0C  = 0x95,

/* USART1 Baud Rate Register High */
  ATM128_UBRR1H  = 0x98,

/* USART1 Baud Rate Register Low*/
  ATM128_UBRR1L  = 0x99,

/* USART1 Control and Status Register B */
  ATM128_UCSR1B  = 0x9A,

/* USART1 Control and Status Register A */
  ATM128_UCSR1A  = 0x9B,

/* USART1 I/O Data Register */
  ATM128_UDR1    = 0x9C,

/* USART1 Control and Status Register C */
  ATM128_UCSR1C  = 0x9D,
};

/* Input Pins, Port F */
#define PINF      _SFR_IO8(0x00)

/* Input Pins, Port E */
#define PINE      _SFR_IO8(0x01)

/* Data Direction Register, Port E */
#define DDRE      _SFR_IO8(0x02)

/* Data Register, Port E */
#define PORTE     _SFR_IO8(0x03)

/* ADC Data Register */
#define ADCW      _SFR_IO16(0x04) /* for backwards compatibility */
#ifndef __ASSEMBLER__
#define ADC       _SFR_IO16(0x04)
#endif
#define ADCL      _SFR_IO8(0x04)
#define ADCH      _SFR_IO8(0x05)

/* ADC Control and status register */
#define ADCSR     _SFR_IO8(0x06)
#define ADCSRA    _SFR_IO8(0x06) /* new name in datasheet (2467E-AVR-05/02) */

/* ADC Multiplexer select */
#define ADMUX     _SFR_IO8(0x07)

/* Analog Comparator Control and Status Register */
#define ACSR      _SFR_IO8(0x08)

/* USART0 Baud Rate Register Low */
#define UBRR0L    _SFR_IO8(0x09)

/* USART0 Control and Status Register B */
#define UCSR0B    _SFR_IO8(0x0A)

/* USART0 Control and Status Register A */
#define UCSR0A    _SFR_IO8(0x0B)

/* USART0 I/O Data Register */
#define UDR0      _SFR_IO8(0x0C)

/* SPI Control Register */
#define SPCR      _SFR_IO8(0x0D)

/* SPI Status Register */
#define SPSR      _SFR_IO8(0x0E)

/* SPI I/O Data Register */
#define SPDR      _SFR_IO8(0x0F)

/* Input Pins, Port D */
#define PIND      _SFR_IO8(0x10)

/* Data Direction Register, Port D */
#define DDRD      _SFR_IO8(0x11)

/* Data Register, Port D */
#define PORTD     _SFR_IO8(0x12)

/* Input Pins, Port C */
#define PINC      _SFR_IO8(0x13)

/* Data Direction Register, Port C */
#define DDRC      _SFR_IO8(0x14)

/* Data Register, Port C */
#define PORTC     _SFR_IO8(0x15)

/* Input Pins, Port B */
#define PINB      _SFR_IO8(0x16)

/* Data Direction Register, Port B */
#define DDRB      _SFR_IO8(0x17)

/* Data Register, Port B */
#define PORTB     _SFR_IO8(0x18)

/* Input Pins, Port A */
#define PINA      _SFR_IO8(0x19)

/* Data Direction Register, Port A */
#define DDRA      _SFR_IO8(0x1A)

/* Data Register, Port A */
#define PORTA     _SFR_IO8(0x1B)

/* 0x1C..0x1F EEPROM */

/* Special Function I/O Register */
#define SFIOR     _SFR_IO8(0x20)

/* Watchdog Timer Control Register */
#define WDTCR     _SFR_IO8(0x21)

/* On-chip Debug Register */
#define OCDR      _SFR_IO8(0x22)

/* Timer2 Output Compare Register */
#define OCR2      _SFR_IO8(0x23)

/* Timer/Counter 2 */
#define TCNT2     _SFR_IO8(0x24)

/* Timer/Counter 2 Control register */
#define TCCR2     _SFR_IO8(0x25)

/* T/C 1 Input Capture Register */
#define ICR1      _SFR_IO16(0x26)
#define ICR1L     _SFR_IO8(0x26)
#define ICR1H     _SFR_IO8(0x27)

/* Timer/Counter1 Output Compare Register B */
#define OCR1B     _SFR_IO16(0x28)
#define OCR1BL    _SFR_IO8(0x28)
#define OCR1BH    _SFR_IO8(0x29)

/* Timer/Counter1 Output Compare Register A */
#define OCR1A     _SFR_IO16(0x2A)
#define OCR1AL    _SFR_IO8(0x2A)
#define OCR1AH    _SFR_IO8(0x2B)

/* Timer/Counter 1 */
#define TCNT1     _SFR_IO16(0x2C)
#define TCNT1L    _SFR_IO8(0x2C)
#define TCNT1H    _SFR_IO8(0x2D)

/* Timer/Counter 1 Control and Status Register */
#define TCCR1B    _SFR_IO8(0x2E)

/* Timer/Counter 1 Control Register */
#define TCCR1A    _SFR_IO8(0x2F)

/* Timer/Counter 0 Asynchronous Control & Status Register */
#define ASSR      _SFR_IO8(0x30)

/* Output Compare Register 0 */
#define OCR0      _SFR_IO8(0x31)

/* Timer/Counter 0 */
#define TCNT0     _SFR_IO8(0x32)

/* Timer/Counter 0 Control Register */
#define TCCR0     _SFR_IO8(0x33)

/* MCU Status Register */
#define MCUSR     _SFR_IO8(0x34)
#define MCUCSR    _SFR_IO8(0x34) /* new name in datasheet (2467E-AVR-05/02) */

/* MCU general Control Register */
#define MCUCR     _SFR_IO8(0x35)

/* Timer/Counter Interrupt Flag Register */
#define TIFR      _SFR_IO8(0x36)

/* Timer/Counter Interrupt MaSK register */
#define TIMSK     _SFR_IO8(0x37)

/* External Interrupt Flag Register */
#define EIFR      _SFR_IO8(0x38)

/* External Interrupt MaSK register */
#define EIMSK     _SFR_IO8(0x39)

/* External Interrupt Control Register B */
#define EICRB     _SFR_IO8(0x3A)

/* RAM Page Z select register */
#define RAMPZ     _SFR_IO8(0x3B)

/* XDIV Divide control register */
#define XDIV      _SFR_IO8(0x3C)

/* 0x3D..0x3E SP */

/* 0x3F SREG */
#define SREG      _SFR_IO8(0x3F)

/* Extended I/O registers */

/* Data Direction Register, Port F */
#define DDRF      _SFR_MEM8(0x61)

/* Data Register, Port F */
#define PORTF     _SFR_MEM8(0x62)

/* Input Pins, Port G */
#define PING      _SFR_MEM8(0x63)

/* Data Direction Register, Port G */
#define DDRG      _SFR_MEM8(0x64)

/* Data Register, Port G */
#define PORTG     _SFR_MEM8(0x65)

/* Store Program Memory Control and Status Register */
#define SPMCR     _SFR_MEM8(0x68)
#define SPMCSR    _SFR_MEM8(0x68) /* new name in datasheet (2467E-AVR-05/02) */

/* External Interrupt Control Register A */
#define EICRA     _SFR_MEM8(0x6A)

/* External Memory Control Register B */
#define XMCRB     _SFR_MEM8(0x6C)

/* External Memory Control Register A */
#define XMCRA     _SFR_MEM8(0x6D)

/* Oscillator Calibration Register */
#define OSCCAL    _SFR_MEM8(0x6F)

/* 2-wire Serial Interface Bit Rate Register */
#define TWBR      _SFR_MEM8(0x70)

/* 2-wire Serial Interface Status Register */
#define TWSR      _SFR_MEM8(0x71)

/* 2-wire Serial Interface Address Register */
#define TWAR      _SFR_MEM8(0x72)

/* 2-wire Serial Interface Data Register */
#define TWDR      _SFR_MEM8(0x73)

/* 2-wire Serial Interface Control Register */
#define TWCR      _SFR_MEM8(0x74)

/* Time Counter 1 Output Compare Register C */
#define OCR1C     _SFR_MEM16(0x78)
#define OCR1CL    _SFR_MEM8(0x78)
#define OCR1CH    _SFR_MEM8(0x79)

/* Timer/Counter 1 Control Register C */
#define TCCR1C    _SFR_MEM8(0x7A)

/* Extended Timer Interrupt Flag Register */
#define ETIFR     _SFR_MEM8(0x7C)

/* Extended Timer Interrupt Mask Register */
#define ETIMSK    _SFR_MEM8(0x7D)

/* Timer/Counter 3 Input Capture Register */
#define ICR3      _SFR_MEM16(0x80)
#define ICR3L     _SFR_MEM8(0x80)
#define ICR3H     _SFR_MEM8(0x81)

/* Timer/Counter 3 Output Compare Register C */
#define OCR3C     _SFR_MEM16(0x82)
#define OCR3CL    _SFR_MEM8(0x82)
#define OCR3CH    _SFR_MEM8(0x83)

/* Timer/Counter 3 Output Compare Register B */
#define OCR3B     _SFR_MEM16(0x84)
#define OCR3BL    _SFR_MEM8(0x84)
#define OCR3BH    _SFR_MEM8(0x85)

/* Timer/Counter 3 Output Compare Register A */
#define OCR3A     _SFR_MEM16(0x86)
#define OCR3AL    _SFR_MEM8(0x86)
#define OCR3AH    _SFR_MEM8(0x87)

/* Timer/Counter 3 Counter Register */
#define TCNT3     _SFR_MEM16(0x88)
#define TCNT3L    _SFR_MEM8(0x88)
#define TCNT3H    _SFR_MEM8(0x89)

/* Timer/Counter 3 Control Register B */
#define TCCR3B    _SFR_MEM8(0x8A)

/* Timer/Counter 3 Control Register A */
#define TCCR3A    _SFR_MEM8(0x8B)

/* Timer/Counter 3 Control Register C */
#define TCCR3C    _SFR_MEM8(0x8C)

/* USART0 Baud Rate Register High */
#define UBRR0H    _SFR_MEM8(0x90)

/* USART0 Control and Status Register C */
#define UCSR0C    _SFR_MEM8(0x95)

/* USART1 Baud Rate Register High */
#define UBRR1H    _SFR_MEM8(0x98)

/* USART1 Baud Rate Register Low*/
#define UBRR1L    _SFR_MEM8(0x99)

/* USART1 Control and Status Register B */
#define UCSR1B    _SFR_MEM8(0x9A)

/* USART1 Control and Status Register A */
#define UCSR1A    _SFR_MEM8(0x9B)

/* USART1 I/O Data Register */
#define UDR1      _SFR_MEM8(0x9C)

/* USART1 Control and Status Register C */
#define UCSR1C    _SFR_MEM8(0x9D)

/* Interrupt vectors */

#define _VECTOR(x) INTERRUPT_##x

#define SIG_INTERRUPT0          _VECTOR(1)
#define SIG_INTERRUPT1          _VECTOR(2)
#define SIG_INTERRUPT2          _VECTOR(3)
#define SIG_INTERRUPT3          _VECTOR(4)
#define SIG_INTERRUPT4          _VECTOR(5)
#define SIG_INTERRUPT5          _VECTOR(6)
#define SIG_INTERRUPT6          _VECTOR(7)
#define SIG_INTERRUPT7          _VECTOR(8)
#define SIG_OUTPUT_COMPARE2     _VECTOR(9)
#define SIG_OVERFLOW2           _VECTOR(10)
#define SIG_INPUT_CAPTURE1      _VECTOR(11)
#define SIG_OUTPUT_COMPARE1A    _VECTOR(12)
#define SIG_OUTPUT_COMPARE1B    _VECTOR(13)
#define SIG_OVERFLOW1           _VECTOR(14)
#define SIG_OUTPUT_COMPARE0     _VECTOR(15)
#define SIG_OVERFLOW0           _VECTOR(16)
#define SIG_SPI                 _VECTOR(17)
#define SIG_USART0_RECV         _VECTOR(18)
#define SIG_UART0_RECV          _VECTOR(18) /* Keep for compatibility */
#define SIG_USART0_DATA         _VECTOR(19)
#define SIG_UART0_DATA          _VECTOR(19) /* Keep for compatibility */
#define SIG_USART0_TRANS        _VECTOR(20)
#define SIG_UART0_TRANS         _VECTOR(20) /* Keep for compatibility */
#define SIG_ADC                 _VECTOR(21)
#define SIG_EEPROM_READY        _VECTOR(22)
#define SIG_COMPARATOR          _VECTOR(23)