pxa27x_registers.h

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#define DTADR(_ch) _PXAREG_OFFSET(&DTADR0,((_ch) << 4))
#define DCMD(_ch) _PXAREG_OFFSET(&DCMD0,((_ch) << 4))


#define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
#define DDADR_STOP	(1 << 0)	/* Stop (read / write) */

#define DRCMR_MAPVLD	(1 << 7)	/* Map Valid Channel */
#define DRCMR_CHLNUM(_ch) ((_ch) & 0x1f)

#define DCSR_RUN	(1 << 31)	/* Run Bit (read / write) */
#define DCSR_NODESCFETCH (1 << 30)	/* No-Descriptor Fetch (read / write) */
#define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enabled */
#define DCSR_EORIRQEN	(1 << 28)	/* End-of-Receive Interrupt Enable */
#define DCSR_EORJMPEN	(1 << 27)	/* Jump to Next Descriptor on EOR */
#define DCSR_EORSTOPEN	(1 << 26)	/* Stop Channel on EOR */
#define DCSR_SETCMPST	(1 << 25)	/* Set Descriptor Compare Status */
#define DCSR_CLRCMPST	(1 << 24)	/* Clear Descriptor Compare Status */
#define DCSR_RASIRQEN	(1 << 23)	/* Request After Channel Stoopped Interrupt Enable */
#define DCSR_MASKRUN	(1 << 22)	/* Mask Run */
#define DCSR_CMPST	(1 << 10)	/* Descriptor Compare Status */
#define DCSR_EORINT	(1 << 9)	/* End of Recieve */
#define DCSR_REQPEND	(1 << 8)	/* Request Pending (read-only) */
#define DCSR_RASINTR	(1 << 4)	/* Request After Channel Stopped */
#define DCSR_STOPINTR	(1 << 3)	/* Stop Interrupt */
#define DCSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write) */
#define DCSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write) */
#define DCSR_BUSERRINTR	(1 << 0)	/* Bus Error Interrupt (read / write) */

#define DRQSR_CLR	(1 << 8)	/* Clear Pending Requests */

#define DCMD_INCSRCADDR	(1 << 31)	/* Source Address Increment Setting. */
#define DCMD_INCTRGADDR	(1 << 30)	/* Target Address Increment Setting. */
#define DCMD_FLOWSRC	(1 << 29)	/* Flow Control by the source. */
#define DCMD_FLOWTRG	(1 << 28)	/* Flow Control by the target. */
#define DCMD_CMPEN	(1 << 25)	/* Descriptor Compare Enable */
#define DCMD_ADDRMODE   (1 << 23)	/* Addressing Mode */
#define DCMD_STARTIRQEN	(1 << 22)	/* Start Interrupt Enable */
#define DCMD_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */
#define DCMD_FLYBYS	(1 << 20)	/* Fly-By Source */
#define DCMD_FLYBYT	(1 << 19)	/* Fly-By Target */
#define DCMD_BURST8	(1 << 16)	/* 8 byte burst */
#define DCMD_BURST16	(2 << 16)	/* 16 byte burst */
#define DCMD_BURST32	(3 << 16)	/* 32 byte burst */
#define DCMD_WIDTH1	(1 << 14)	/* 1 byte width */
#define DCMD_WIDTH2	(2 << 14)	/* 2 byte width (HalfWord) */
#define DCMD_WIDTH4	(3 << 14)	/* 4 byte width (Word) */
#define DCMD_SIZE(_x)	(((_x) & 0x3)<<16)	/* Burst Size */
#define DCMD_MAXSIZE    DCMD_SIZE(3)
#define DCMD_WIDTH(_x)	(((_x) & 0x3)<<14)	/* Peripheral Width  */
#define DCMD_MAXWIDTH   DCMD_WIDTH(3)
#define DCMD_LEN(_x)	(((_x) & 0x1fff))	/* Length of transfer (0 for descriptor ops) */
#define DCMD_MAXLEN     DCMD_LEN(0x1fff)

#define DMAREQ_DREQ0		(0)	
#define DMAREQ_DREQ1		(1)	
#define DMAREQ_I2S_RECV		(2)	
#define DMAREQ_I2S_XMT		(3)	
#define DMAREQ_BTUART_RECV	(4)	
#define DMAREQ_BTUART_XMT	(5)	
#define DMAREQ_FFUAR_RECV	(6)	
#define DMAREQ_FFUART_XMT	(7)	
#define DMAREQ_AC97_MICR	(8)	
#define DMAREQ_AC97_MODEM_RECV	(9)	
#define DMAREQ_AC97_MODEM_XMT	(10)	
#define DMAREQ_AC97_AUDIO_RECV	(11)	
#define DMAREQ_AC97_AUDIO_XMT	(12)	
#define DMAREQ_SSP1_RECV	(13)	
#define DMAREQ_SSP1_XMT		(14)	
#define DMAREQ_SSP2_RECV	(15)	
#define DMAREQ_SSP2_XMT		(16)	
#define DMAREQ_ICP_RECV		(17)	
#define DMAREQ_ICP_XMT		(18)	
#define DMAREQ_STUART_RECV	(19)	
#define DMAREQ_STUART_XMT	(20)	
#define DMAREQ_MMCSDIO_RECV	(21)	
#define DMAREQ_MMCSDIO_XMT	(22)	

#define DMAREQ_USB_EP_0		(24)	
#define DMAREQ_USB_EP_A		(25)	
#define DMAREQ_USB_EP_B		(26)	
#define DMAREQ_USB_EP_C		(27)	
#define DMAREQ_USB_EP_D		(28)	
#define DMAREQ_USB_EP_E		(29)	
#define DMAREQ_USB_EP_F		(30)	
#define DMAREQ_USB_EP_G		(31)	
#define DMAREQ_USB_EP_H		(32)	
#define DMAREQ_USB_EP_I		(33)	
#define DMAREQ_USB_EP_J		(34)	
#define DMAREQ_USB_EP_K		(35)	
#define DMAREQ_USB_EP_L		(36)	
#define DMAREQ_USB_EP_M		(37)	
#define DMAREQ_USB_EP_N		(38)	
#define DMAREQ_USB_EP_P		(39)	
#define DMAREQ_USB_EP_Q		(40)	
#define DMAREQ_USB_EP_R		(41)	
#define DMAREQ_USB_EP_S		(42)	
#define DMAREQ_USB_EP_T		(43)	
#define DMAREQ_USB_EP_U		(44)	
#define DMAREQ_USB_EP_V		(45)	
#define DMAREQ_USB_EP_W		(46)	
#define DMAREQ_USB_EP_X		(47)	
#define DMAREQ_MSL_RECV_1	(48)	
#define DMAREQ_MSL_XMT_1	(49)	
#define DMAREQ_MSL_RECV_2	(50)	
#define DMAREQ_MSL_XMT_2	(51)	
#define DMAREQ_MSL_RECV_3	(52)	
#define DMAREQ_MSL_XMT_3	(53)	
#define DMAREQ_MSL_RECV_4	(54)	
#define DMAREQ_MSL_XMT_4	(55)	
#define DMAREQ_MSL_RECV_5	(56)	
#define DMAREQ_MSL_XMT_5	(57)	
#define DMAREQ_MSL_RECV_6	(58)	
#define DMAREQ_MSL_XMT_6	(59)	
#define DMAREQ_MSL_RECV_7	(60)	
#define DMAREQ_MSL_XMT_7	(61)	
#define DMAREQ_USIM_RECV	(62)	
#define DMAREQ_USIM_XMT		(63)	
#define DMAREQ_MEMSTICK_RECV	(64)	
#define DMAREQ_MEMSTICK_XMT	(65)	
#define DMAREQ_SSP3_RECV	(66)	
#define DMAREQ_SSP3_XMT		(67)	
#define DMAREQ_CIF_RECV_0	(68)	
#define DMAREQ_CIF_RECV_1	(69)	
#define DMAREQ_CIF_RECV_2	(70)	
#define DMAREQ_DREQ2     	(74)	



/******************************************************************************/
/* Full-Function UART */
/******************************************************************************/
#define FFRBR	_PXAREG(0x40100000) /* Receive Buffer register 10-13 */
#define FFTHR	_PXAREG(0x40100000) /* Transmit Holding register 10-14 */
#define FFDLL	_PXAREG(0x40100000) /* Divisor Latch register, low byte 10-14 */
#define FFIER	_PXAREG(0x40100004) /* Interrupt Enable register 10-15 */
#define FFDLH	_PXAREG(0x40100004) /* Divisor Latch register, high byte 10-14 */
#define FFIIR	_PXAREG(0x40100008) /* Interrupt ID register 10-17 */
#define FFFCR	_PXAREG(0x40100008) /* FIFO Control register 10-19 */
#define FFLCR	_PXAREG(0x4010000C) /* Line Control register 10-25 */
#define FFMCR	_PXAREG(0x40100010) /* Modem Control register 10-29 */
#define FFLSR	_PXAREG(0x40100014) /* Line Status register 10-26 */
#define FFMSR	_PXAREG(0x40100018) /* Modem Status register 10-31 */
#define FFSPR	_PXAREG(0x4010001C) /* Scratch Pad register 10-33 */
#define FFISR	_PXAREG(0x40100020) /* Infrared Select register 10-33 */
#define FFFOR	_PXAREG(0x40100024) /* Receive FIFO Occupancy register 10-22 */
#define FFABR	_PXAREG(0x40100028) /* Auto-baud Control register 10-23 */
#define FFACR	_PXAREG(0x4010002C) /* Auto-baud Count register 10-24 */


/******************************************************************************/
/* Bluetooth UART */
/******************************************************************************/
#define BTRBR	_PXAREG(0x40200000) /* Receive Buffer register 10-13 */
#define BTTHR	_PXAREG(0x40200000) /* Transmit Holding register 10-14 */
#define BTDLL	_PXAREG(0x40200000) /* Divisor Latch register, low byte 10-14 */
#define BTIER	_PXAREG(0x40200004) /* Interrupt Enable register 10-15 */
#define BTDLH	_PXAREG(0x40200004) /* Divisor Latch register, high byte 10-14 */
#define BTIIR	_PXAREG(0x40200008) /* Interrupt ID register 10-17 */
#define BTFCR	_PXAREG(0x40200008) /* FIFO Control register 10-19 */
#define BTLCR	_PXAREG(0x4020000C) /* Line Control register 10-25 */
#define BTMCR	_PXAREG(0x40200010) /* Modem Control register 10-29 */
#define BTLSR	_PXAREG(0x40200014) /* Line Status register 10-26 */
#define BTMSR	_PXAREG(0x40200018) /* Modem Status register 10-31 */
#define BTSPR	_PXAREG(0x4020001C) /* Scratch Pad register 10-33 */
#define BTISR	_PXAREG(0x40200020) /* Infrared Select register 10-33 */
#define BTFOR	_PXAREG(0x40200024) /* Receive FIFO Occupancy register 10-22 */
#define BTABR	_PXAREG(0x40200028) /* Auto-Baud Control register 10-23 */
#define BTACR	_PXAREG(0x4020002C) /* Auto-Baud Count register 10-24 */

#define IER_DMAE	(1 << 7)	/* DMA Requests Enable */
#define IER_UUE		(1 << 6)	/* UART Unit Enable */
#define IER_NRZE	(1 << 5)	/* NRZ coding Enable */
#define IER_RTIOE	(1 << 4)	/* Receiver Time Out Interrupt Enable */
#define IER_MIE		(1 << 3)	/* Modem Interrupt Enable */
#define IER_RLSE	(1 << 2)	/* Receiver Line Status Interrupt Enable */
#define IER_TIE		(1 << 1)	/* Transmit Data request Interrupt Enable */
#define IER_RAVIE	(1 << 0)	/* Receiver Data Available Interrupt Enable */

#define IIR_FIFOES1	(1 << 7)	/* FIFO Mode Enable Status */
#define IIR_FIFOES0	(1 << 6)	/* FIFO Mode Enable Status */
#define IIR_TOD		(1 << 3)	/* Time Out Detected */
#define IIR_IID_MASK	(0x3 << 1)	/* Interrupt Source Encoded */
#define IIR_IP		(1 << 0)	/* Interrupt Pending (active low) */

#define FCR_ITL(_x)	((_x) << 6)	/* Interrupt Trigger Level */
#define FCR_BUS		(1 << 5)	/* 32-Bit Peripheral Bus */
#define FCR_TRAIL	(1 << 4)	/* Trailing Bytes */
#define FCR_TIL		(1 << 3)	/* Transmitter Interrupt Level */
#define FCR_RESETTF	(1 << 2)	/* Reset Transmitter FIFO */
#define FCR_RESETRF	(1 << 1)	/* Reset Receiver FIFO */
#define FCR_TRFIFOE	(1 << 0)	/* Transmit and Receive FIFO Enable */

#define ABR_ABT		(1 << 3)	/* Auto-Baud Rate Calculation */
#define ABR_ABUP	(1 << 2)	/* Auto-Baud Programmer */
#define ABR_ABLIE	(1 << 1)	/* Auto-Baud Interrupt */
#define ABR_ABE		(1 << 0)	/* Auto-Baud Enable */