iom16c62p.h

tinyos-2.x.rar

union st_cse {               /* union CSE    	   					*/
   struct {             	 /* Bit  Access 		   				*/
     unsigned char CSE00W:1; /* CS0~ wait expansion bit */
     unsigned char CSE01W:1; /* CS0~ wait expansion bit */
     unsigned char CSE10W:1; /* CS1~ wait expansion bit */
     unsigned char CSE11W:1; /* CS1~ wait expansion bit */
     unsigned char CSE20W:1; /* CS2~ wait expansion bit */
     unsigned char CSE21W:1; /* CS2~ wait expansion bit */
     unsigned char CSE30W:1; /* CS3~ wait expansion bit */
     unsigned char CSE31W:1; /* CS3~ wait expansion bit */
   } BIT;   		    	 /*        						    	*/
     unsigned char BYTE;     /*  Byte Access 						*/
};                           /* Chip select expansion control register    */

/*------------------------------------------------------
   PLL control register 0 //0x001C
-----------------------------------------------------*/
union st_plc0 {               /* union      	   					*/
   struct {             	 /* Bit  Access 		   				*/
     unsigned char PLC00:1; /* Programmable counter select bit */
     unsigned char PLC01:1; /* Programmable counter select bit */
     unsigned char PLC02:1; /* Programmable counter select bit */
     unsigned char      :1; /* Nothing assigned */
     unsigned char      :1; /* Reserved bit,set to one */
     unsigned char      :1; /* Reserved bit,set to zero */
     unsigned char      :1; /* Reserved bit,set to zero */
     unsigned char PLC07:1; /* Operation enable bit */
   } BIT;   		    	 /*        						    	*/
     unsigned char BYTE;     /*  Byte Access 						*/
};                           /* PLL control register 0    */

/*------------------------------------------------------
   Processor mode register 2 //0x001E
-----------------------------------------------------*/
union st_pm2 {               /* union      	   					                   */
   struct {             	 /* Bit  Access 		   				               */
     unsigned char PM2_0:1; /* Specifying wait when accessing SFR at PLL operation */
     unsigned char PM2_1:1; /* System clock protective bit */
     unsigned char PM2_2:1; /* WDT count source protective bit */
     unsigned char      :1; /* Reserved bit,set to zero */
     unsigned char      :1; /* Reserved bit,set to zero */
     unsigned char      :1; /* Nothing assigned */
     unsigned char      :1; /* Nothing assigned */
     unsigned char      :1; /* Nothing assigned */
   } BIT;   		    	 /*        						    	*/
     unsigned char BYTE;     /*  Byte Access 						*/
};                           /* Processor mode register 2    */

/*------------------------------------------------------
   Power supply down detection register //0x001F
-----------------------------------------------------*/
union st_d4int {               /* union      	   					                   */
   struct {             	 /* Bit  Access 		   				               */
     unsigned char D40:1; /* Power supply down detection interrupt enable bit */
     unsigned char D41:1; /* STOP mode deactivation control bit */
     unsigned char D42:1; /* Power supply change detection flag */
     unsigned char D43:1; /* WDT overflow detect flag */
     unsigned char DF0:1; /* Sampling clock select bit */
     unsigned char DF1:1; /* Sampling clock select bit */
     unsigned char    :1; /* Nothing assigned */
     unsigned char    :1; /* Nothing assigned */
   } BIT;   		    	 /*        						    	*/
     unsigned char BYTE;     /*  Byte Access 						*/
};                           /* Power supply down detection register   */

/*------------------------------------------------------
   DMA0 source pointer //0x0020
-----------------------------------------------------*/
union st_sar0 {
   struct{
	unsigned char SAR01;     /* DMA0 source pointer low  8 bit 				 */
	unsigned char SAR0M;     /* DMA0 source pointer mid  8 bit 				 */
	unsigned char SAR0H;     /* DMA0 source pointer high 8 bit 				 */
	unsigned char NC;        /* non use 									 */
   } BYTE;				 	 /* Byte access									 */
   unsigned long   DWORD;	 /*	Word Access									 */
};							 /* DMA0 source pointer 32 bit				 	 */

/*------------------------------------------------------
   DMA1 source pointer //0x0030
-----------------------------------------------------*/
union st_sar1 {
   struct{
	unsigned char SAR11;     /* DMA1 source pointer low  8 bit 				 */
	unsigned char SAR1M;     /* DMA1 source pointer mid  8 bit 				 */
	unsigned char SAR1H;     /* DMA1 source pointer high 8 bit 				 */
	unsigned char NC;        /* non use 									 */
   } BYTE;					 /* Byte access									 */
   unsigned long   DWORD;	 /* Word Access									 */
};					         /* DMA1 source pointer 32 bit				 	 */

/*------------------------------------------------------
   DMA0 destination pointer //0x0024
-----------------------------------------------------*/
union st_dar0 {				 /* DMA0 destination pointer 32 bit	   			 */
   struct{
	unsigned char DAR0L;     /* DMA0 destination pointer low  8 bit  		 */
	unsigned char DAR0M;     /* DMA0 destination pointer mid  8 bit     	 */
	unsigned char DAR0H;     /* DMA0 destination pointer high 8 bit  		 */
	unsigned char NC;        /* non use 							   		 */
   } BYTE;					 /* Byte access						   			 */
    unsigned long DWORD;	 /* Word Access						   			 */
};

/*------------------------------------------------------
  DMA1 destination pointer //0x0034
-----------------------------------------------------*/
union st_dar1 {				  /* DMA1 destination pointer 32 bit			 */
   struct{
	unsigned char DAR1L;     /* DMA1 destination pointer low  8 bit			 */
	unsigned char DAR1M;     /* DMA1 destination pointer mid  8 bit			 */
	unsigned char DAR1H;     /* DMA1 destination pointer high 8 bit			 */
	unsigned char NC;        /* non use 									 */
   } BYTE;					 /* Byte access									 */
   unsigned long   DWORD;	 /* Word Access									 */
};

/*------------------------------------------------------
  DMA0 transfer counter //0x0028
-----------------------------------------------------*/
union st_tcr0 {			  	 /* DMA0 transfer counter 16 bit 	 			 */
   struct{
	unsigned char TCR0L;     /* DMA0 transfer counter low  8 bit 			 */
	unsigned char TCR0H;     /* DMA0 transfer counter high 8 bit 			 */
   } BYTE;					 /* Byte access					     			 */
   unsigned short   WORD;	 /* Word Access					     			 */
};

/*------------------------------------------------------
  DMA1 transfer counter //0x0038
-----------------------------------------------------*/
union st_tcr1 {				  /* DMA1 transfer counter 16 bit 	   			 */
   struct{
	unsigned char TCR1L;     /* DMA1 transfer counter low  8 bit   			 */
	unsigned char TCR1H;     /* DMA1 transfer counter high 8 bit   			 */
   } BYTE;					 /* Byte access					       			 */
   unsigned short WORD;	     /* Word Access					       			 */
};

/*------------------------------------------------------
    DMA0 control register //0x002c
------------------------------------------------------*/
union st_dm0con {		       /* DMA0 control register				*/
   struct{
     unsigned char    DMBIT:1; /* Transfer unit bit select bit 				*/
     unsigned char    DMASL:1; /* Repeat transfer mode select bit 			*/
     unsigned char    DMAS :1; /* DMA request bit 							*/
     unsigned char    DMAE :1; /* DMA enable bit 							*/
     unsigned char    DSD  :1; /* Source address direction select bit   	*/
     unsigned char    DAD  :1; /* Destination address direction select bit  */
     unsigned char    	   :1;
     unsigned char         :1;
   }BIT;
    unsigned char  BYTE;
};

/*------------------------------------------------------
    DMA1 control register //0x003c
------------------------------------------------------*/
union st_dm1con {		/*    DMA1 control register union */
    struct{
     unsigned char    DMBIT:1; /* Transfer unit bit select bit 				*/
     unsigned char    DMASL:1; /* Repeat transfer mode select bit 			*/
     unsigned char    DMAS :1; /* DMA request bit 							*/
     unsigned char    DMAE :1; /* DMA enable bit 							*/
     unsigned char    DSD  :1; /* Source address direction select bit  		*/
     unsigned char    DAD  :1; /* Destination address direction select bit  */
     unsigned char    	   :1; /*Nothing assigned */
     unsigned char         :1; /*Nothing assigned */
    }BIT;
    unsigned char  BYTE;
};

union st_icr {		     	   /*    interrupt control registers	  */
    struct{
     unsigned char    ILVL0:1; /* Interrupt priority level select bit */
     unsigned char    ILVL1:1; /* Interrupt priority level select bit */
     unsigned char    ILVL2:1; /* Interrupt priority level select bit */
     unsigned char    IR   :1; /* Interrupt request bit 			  */
     unsigned char    POL  :1; /* Polarity select bit 				  */
     unsigned char         :1; /* Reserved bit, set to 0              */
     unsigned char    	   :1; /* Nothing assigned					  */
     unsigned char         :1; /* Nothing assigned					  */
    }BIT;
    unsigned char    BYTE;
};

union st_icr1 {		     	   /*    interrupt control registers	  */
    struct{
     unsigned char    ILVL0:1; /* Interrupt priority level select bit */
     unsigned char    ILVL1:1; /* Interrupt priority level select bit */
     unsigned char    ILVL2:1; /* Interrupt priority level select bit */
     unsigned char    IR   :1; /* Interrupt request bit 			  */
     unsigned char         :1; /* Nothing assigned					  */
     unsigned char         :1; /* Nothing assigned					  */
     unsigned char    	   :1; /* Nothing assigned					  */
     unsigned char         :1; /* Nothing assigned					  */
    }BIT;
    unsigned char    BYTE;
};

/*------------------------------------------------------
     bcnic //0x004a
------------------------------------------------------*/
union st_bcnic {					/*    interrupt control registers*/
    struct{
     unsigned char    ILVL0_BCNIC:1;/* Interrupt priority level select bit */
     unsigned char    ILVL1_BCNIC:1;/* Interrupt priority level select bit */
     unsigned char    ILVL2_BCNIC:1;/* Interrupt priority level select bit */
     unsigned char    IR_BCNIC   :1;/* Interrupt request bit */
     unsigned char    		     :1;
     unsigned char               :1;
     unsigned char               :1;
     unsigned char               :1;
    }BIT;
    unsigned char    BYTE;
};

/*------------------------------------------------------
     dm0ic //0x004b
------------------------------------------------------*/
union st_dm0ic {					/*    interrupt control registers*/
    struct{
     unsigned char    ILVL0_DM0IC:1;/* Interrupt priority level select bit */
     unsigned char    ILVL1_DM0IC:1;/* Interrupt priority level select bit */
     unsigned char    ILVL2_DM0IC:1;/* Interrupt priority level select bit */
     unsigned char    IR_DM0IC   :1;/* Interrupt request bit			   */
     unsigned char    		     :1;
     unsigned char               :1;
     unsigned char               :1;
     unsigned char               :1;
    }BIT;
    unsigned char    BYTE;
};

/*------------------------------------------------------
    Flash identification register //0x01b4
------------------------------------------------------*/
union st_fidr {		           /*    Flash identification register         */
    struct{
     unsigned char    FIDR0:1; /* Flash identification value */
     unsigned char    FIDR1:1; /* Flash identification value */
     unsigned char         :1; /* Nothing assigned							*/
     unsigned char         :1; /* Nothing assigned							*/
     unsigned char         :1; /* Nothing assigned                  		*/
     unsigned char         :1; /* Nothing assigned                          */
     unsigned char    	   :1; /* Nothing assigned */
     unsigned char         :1; /* Nothing assigned */
    }BIT;
    unsigned char  BYTE;
};