📄 stm32_eth.h
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/**
* @brief Bit definition of RDES1 register
*/
#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
/**
* @brief Bit definition of RDES2 register
*/
#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
/**
* @brief Bit definition of RDES3 register
*/
#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
/**--------------------------------------------------------------------------**/
/**
* @brief Desciption of common PHY registers
*/
/**--------------------------------------------------------------------------**/
/**
* @}
*/
/** @defgroup PHY_Read_write_Timeouts
* @{
*/
#define PHY_READ_TO ((uint32_t)0x0004FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0004FFFF)
/**
* @}
*/
/** @defgroup PHY_Reset_Delay
* @{
*/
#define PHY_ResetDelay ((uint32_t)0x000FFFFF)
/**
* @}
*/
/** @defgroup PHY_Config_Delay
* @{
*/
#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF)
/**
* @}
*/
/** @defgroup PHY_Register_address
* @{
*/
#define PHY_BCR 0 /*!< Tranceiver Basic Control Register */
#define PHY_BSR 1 /*!< Tranceiver Basic Status Register */
/**
* @}
*/
/** @defgroup PHY_basic_Control_register
* @{
*/
#define PHY_Reset ((u16)0x8000) /*!< PHY Reset */
#define PHY_Loopback ((u16)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((u16)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((u16)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((u16)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((u16)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AutoNegotiation ((u16)0x1000) /*!< Enable auto-negotiation function */
#define PHY_Restart_AutoNegotiation ((u16)0x0200) /*!< Restart auto-negotiation function */
#define PHY_Powerdown ((u16)0x0800) /*!< Select the power down mode */
#define PHY_Isolate ((u16)0x0400) /*!< Isolate PHY from MII */
/**
* @}
*/
/** @defgroup PHY_basic_status_register
* @{
*/
#define PHY_AutoNego_Complete ((u16)0x0020) /*!< Auto-Negotioation process completed */
#define PHY_Linked_Status ((u16)0x0004) /*!< Valid link established */
#define PHY_Jabber_detection ((u16)0x0002) /*!< Jabber condition detected */
/**
* @}
*/
/** @defgroup PHY_status_register
* @{
*/
/* The PHY status register value change from a PHY to another so the user have
to update this value depending on the used external PHY */
/**
* @brief For LAN8700
*/
//#define PHY_SR 31 /*!< Tranceiver Status Register */
/**
* @brief For DP83848
*/
#define PHY_SR 16 /*!< Tranceiver Status Register */
/* The Speed and Duplex mask values change from a PHY to another so the user have to update
this value depending on the used external PHY */
/**
* @brief For LAN8700
*/
//#define PHY_Speed_Status ((u16)0x0004) /*!< Configured information of Speed: 10Mbps */
//#define PHY_Duplex_Status ((u16)0x0010) /*!< Configured information of Duplex: Full-duplex */
/**
* @brief For DP83848
*/
#define PHY_Speed_Status ((u16)0x0002) /*!< Configured information of Speed: 10Mbps */
#define PHY_Duplex_Status ((u16)0x0004) /*!< Configured information of Duplex: Full-duplex */
#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \
((REG) == PHY_BSR) || \
((REG) == PHY_SR))
/**--------------------------------------------------------------------------**/
/**
* @brief MAC defines
*/
/**--------------------------------------------------------------------------**/
/**
* @}
*/
/** @defgroup ETH_AutoNegotiation
* @{
*/
#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001)
#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000)
#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \
((CMD) == ETH_AutoNegotiation_Disable))
/**
* @}
*/
/** @defgroup ETH_watchdog
* @{
*/
#define ETH_Watchdog_Enable ((uint32_t)0x00000000)
#define ETH_Watchdog_Disable ((uint32_t)0x00800000)
#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \
((CMD) == ETH_Watchdog_Disable))
/**
* @}
*/
/** @defgroup ETH_Jabber
* @{
*/
#define ETH_Jabber_Enable ((uint32_t)0x00000000)
#define ETH_Jabber_Disable ((uint32_t)0x00400000)
#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \
((CMD) == ETH_Jabber_Disable))
/**
* @}
*/
/** @defgroup ETH_Inter_Frame_Gap
* @{
*/
#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \
((GAP) == ETH_InterFrameGap_88Bit) || \
((GAP) == ETH_InterFrameGap_80Bit) || \
((GAP) == ETH_InterFrameGap_72Bit) || \
((GAP) == ETH_InterFrameGap_64Bit) || \
((GAP) == ETH_InterFrameGap_56Bit) || \
((GAP) == ETH_InterFrameGap_48Bit) || \
((GAP) == ETH_InterFrameGap_40Bit))
/**
* @}
*/
/** @defgroup ETH_Carrier_Sense
* @{
*/
#define ETH_CarrierSense_Enable ((uint32_t)0x00000000)
#define ETH_CarrierSense_Disable ((uint32_t)0x00010000)
#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \
((CMD) == ETH_CarrierSense_Disable))
/**
* @}
*/
/** @defgroup ETH_Speed
* @{
*/
#define ETH_Speed_10M ((uint32_t)0x00000000)
#define ETH_Speed_100M ((uint32_t)0x00004000)
#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \
((SPEED) == ETH_Speed_100M))
/**
* @}
*/
/** @defgroup ETH_Receive_Own
* @{
*/
#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000)
#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000)
#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \
((CMD) == ETH_ReceiveOwn_Disable))
/**
* @}
*/
/** @defgroup ETH_Loop_back_Mode
* @{
*/
#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000)
#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000)
#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \
((CMD) == ETH_LoopbackMode_Disable))
/**
* @}
*/
/** @defgroup ETH_Duplex_mode
* @{
*/
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