📄 at91m55800a.h
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AT91_REG Reserved0[3]; //
AT91_REG SF_PMR; // Protect Mode Register
} AT91S_SF, *AT91PS_SF;
// -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register --------
#define AT91C_SF_VERSION ((unsigned int) 0x1F << 0) // (SF) Version of the chip
#define AT91C_SF_BIT5 ((unsigned int) 0x1 << 5) // (SF) Hardwired at 0
#define AT91C_SF_BIT6 ((unsigned int) 0x1 << 6) // (SF) Hardwired at 1
#define AT91C_SF_BIT7 ((unsigned int) 0x1 << 7) // (SF) Hardwired at 0
#define AT91C_SF_NVPSIZ ((unsigned int) 0xF << 8) // (SF) Nonvolatile Program Memory Size
#define AT91C_SF_NVPSIZ_NONE ((unsigned int) 0x0 << 8) // (SF) None
#define AT91C_SF_NVPSIZ_32K ((unsigned int) 0x3 << 8) // (SF) 32K Bytes
#define AT91C_SF_NVPSIZ_64K ((unsigned int) 0x5 << 8) // (SF) 64K Bytes
#define AT91C_SF_NVPSIZ_128K ((unsigned int) 0x7 << 8) // (SF) 128K Bytes
#define AT91C_SF_NVPSIZ_256K ((unsigned int) 0x11 << 8) // (SF) 256K Bytes
#define AT91C_SF_NVDSIZ ((unsigned int) 0xF << 12) // (SF) Nonvolatile Data Memory Size
#define AT91C_SF_NVDSIZ_NONE ((unsigned int) 0x0 << 12) // (SF) None
#define AT91C_SF_VDSIZ ((unsigned int) 0xF << 16) // (SF) Volatile Data Memory Size
#define AT91C_SF_VDSIZ_NONE ((unsigned int) 0x0 << 16) // (SF) None
#define AT91C_SF_VDSIZ_1K ((unsigned int) 0x3 << 16) // (SF) 1K Bytes
#define AT91C_SF_VDSIZ_2K ((unsigned int) 0x5 << 16) // (SF) 2K Bytes
#define AT91C_SF_VDSIZ_4K ((unsigned int) 0x7 << 16) // (SF) 4K Bytes
#define AT91C_SF_VDSIZ_8K ((unsigned int) 0x11 << 16) // (SF) 8K Bytes
#define AT91C_SF_ARCH ((unsigned int) 0xFF << 20) // (SF) Chip Architecture
#define AT91C_SF_ARCH_AT91x40 ((unsigned int) 0x28 << 20) // (SF) AT91x40yyy
#define AT91C_SF_ARCH_AT91x55 ((unsigned int) 0x37 << 20) // (SF) AT91x55yyy
#define AT91C_SF_ARCH_AT91x63 ((unsigned int) 0x3F << 20) // (SF) AT91x63yyy
#define AT91C_SF_NVPTYP ((unsigned int) 0x7 << 28) // (SF) Nonvolatile Program Memory Type
#define AT91C_SF_NVPTYP_NVPTYP_M ((unsigned int) 0x1 << 28) // (SF) 'M' Series or 'F' Series
#define AT91C_SF_NVPTYP_NVPTYP_R ((unsigned int) 0x4 << 28) // (SF) 'R' Series
#define AT91C_SF_EXT ((unsigned int) 0x1 << 31) // (SF) Extension Flag
// -------- SF_RSR : (SF Offset: 0x8) Reset Status Information --------
#define AT91C_SF_RESET ((unsigned int) 0xFF << 0) // (SF) Cause of Reset
#define AT91C_SF_RESET_WD ((unsigned int) 0x35) // (SF) Internal Watchdog
#define AT91C_SF_RESET_EXT ((unsigned int) 0x6C) // (SF) External Pin
// -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register --------
#define AT91C_SF_AIC ((unsigned int) 0x1 << 5) // (SF) AIC Protect Mode Enable
#define AT91C_SF_PMRKEY ((unsigned int) 0xFFFF << 16) // (SF) Protect Mode Register Key
// *****************************************************************************
// SOFTWARE API DEFINITION FOR External Bus Interface
// *****************************************************************************
typedef struct _AT91S_EBI {
AT91_REG EBI_CSR[8]; // Chip-select Register
AT91_REG EBI_RCR; // Remap Control Register
AT91_REG EBI_MCR; // Memory Control Register
} AT91S_EBI, *AT91PS_EBI;
// -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register --------
#define AT91C_EBI_DBW ((unsigned int) 0x3 << 0) // (EBI) Data Bus Width
#define AT91C_EBI_DBW_16 ((unsigned int) 0x1) // (EBI) 16-bit data bus width
#define AT91C_EBI_DBW_8 ((unsigned int) 0x2) // (EBI) 8-bit data bus width
#define AT91C_EBI_NWS ((unsigned int) 0x7 << 2) // (EBI) Number of wait states
#define AT91C_EBI_NWS_1 ((unsigned int) 0x0 << 2) // (EBI) 1 wait state
#define AT91C_EBI_NWS_2 ((unsigned int) 0x1 << 2) // (EBI) 2 wait state
#define AT91C_EBI_NWS_3 ((unsigned int) 0x2 << 2) // (EBI) 3 wait state
#define AT91C_EBI_NWS_4 ((unsigned int) 0x3 << 2) // (EBI) 4 wait state
#define AT91C_EBI_NWS_5 ((unsigned int) 0x4 << 2) // (EBI) 5 wait state
#define AT91C_EBI_NWS_6 ((unsigned int) 0x5 << 2) // (EBI) 6 wait state
#define AT91C_EBI_NWS_7 ((unsigned int) 0x6 << 2) // (EBI) 7 wait state
#define AT91C_EBI_NWS_8 ((unsigned int) 0x7 << 2) // (EBI) 8 wait state
#define AT91C_EBI_WSE ((unsigned int) 0x1 << 5) // (EBI) Wait State Enable
#define AT91C_EBI_PAGES ((unsigned int) 0x3 << 7) // (EBI) Pages Size
#define AT91C_EBI_PAGES_1M ((unsigned int) 0x0 << 7) // (EBI) 1M Byte
#define AT91C_EBI_PAGES_4M ((unsigned int) 0x1 << 7) // (EBI) 4M Byte
#define AT91C_EBI_PAGES_16M ((unsigned int) 0x2 << 7) // (EBI) 16M Byte
#define AT91C_EBI_PAGES_64M ((unsigned int) 0x3 << 7) // (EBI) 64M Byte
#define AT91C_EBI_TDF ((unsigned int) 0x7 << 9) // (EBI) Data Float Output Time
#define AT91C_EBI_TDF_0 ((unsigned int) 0x0 << 9) // (EBI) 1 TDF
#define AT91C_EBI_TDF_1 ((unsigned int) 0x1 << 9) // (EBI) 2 TDF
#define AT91C_EBI_TDF_2 ((unsigned int) 0x2 << 9) // (EBI) 3 TDF
#define AT91C_EBI_TDF_3 ((unsigned int) 0x3 << 9) // (EBI) 4 TDF
#define AT91C_EBI_TDF_4 ((unsigned int) 0x4 << 9) // (EBI) 5 TDF
#define AT91C_EBI_TDF_5 ((unsigned int) 0x5 << 9) // (EBI) 6 TDF
#define AT91C_EBI_TDF_6 ((unsigned int) 0x6 << 9) // (EBI) 7 TDF
#define AT91C_EBI_TDF_7 ((unsigned int) 0x7 << 9) // (EBI) 8 TDF
#define AT91C_EBI_BAT ((unsigned int) 0x1 << 12) // (EBI) Byte Access Type
#define AT91C_EBI_CSEN ((unsigned int) 0x1 << 13) // (EBI) Chip Select Enable
#define AT91C_EBI_BA ((unsigned int) 0xFFF << 20) // (EBI) Base Address
// -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register --------
#define AT91C_EBI_RCB ((unsigned int) 0x1 << 0) // (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices.
// -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register --------
#define AT91C_EBI_ALE ((unsigned int) 0x7 << 0) // (EBI) Address Line Enable
#define AT91C_EBI_ALE_16M ((unsigned int) 0x0) // (EBI) Valid Address Bits = A20, A21, A22, A23 Max Addressable Space = 16M Bytes Valid Chip Select=None
#define AT91C_EBI_ALE_8M ((unsigned int) 0x4) // (EBI) Valid Address Bits = A20, A21, A22 Max Addressable Space = 8M Bytes Valid Chip Select = CS4
#define AT91C_EBI_ALE_4M ((unsigned int) 0x5) // (EBI) Valid Address Bits = A20, A21 Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5
#define AT91C_EBI_ALE_2M ((unsigned int) 0x6) // (EBI) Valid Address Bits = A20 Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6
#define AT91C_EBI_ALE_1M ((unsigned int) 0x7) // (EBI) Valid Address Bits = None Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7
#define AT91C_EBI_DRP ((unsigned int) 0x1 << 4) // (EBI)
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91M55800A
// *****************************************************************************
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector egister
#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode egister
#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command egister
// ========== Register definition for WD peripheral ==========
#define AT91C_WD_SR ((AT91_REG *) 0xFFFF800C) // (WD) Status Register
#define AT91C_WD_CMR ((AT91_REG *) 0xFFFF8004) // (WD) Clock Mode Register
#define AT91C_WD_CR ((AT91_REG *) 0xFFFF8008) // (WD) Control Register
#define AT91C_WD_OMR ((AT91_REG *) 0xFFFF8000) // (WD) Overflow Mode Register
// ========== Register definition for APMC peripheral ==========
#define AT91C_APMC_SR ((AT91_REG *) 0xFFFF4030) // (APMC) Status Register
#define AT91C_APMC_PCR ((AT91_REG *) 0xFFFF4028) // (APMC) Power Control Register
#define AT91C_APMC_CGMR ((AT91_REG *) 0xFFFF4020) // (APMC) Clock Generator Mode Register
#define AT91C_APMC_PCSR ((AT91_REG *) 0xFFFF4018) // (APMC) Peripheral Clock Status Register
#define AT91C_APMC_IMR ((AT91_REG *) 0xFFFF403C) // (APMC) Interrupt Mask Register
#define AT91C_APMC_IER ((AT91_REG *) 0xFFFF4034) // (APMC) Interrupt Enable Register
#define AT91C_APMC_PMR ((AT91_REG *) 0xFFFF402C) // (APMC) Power Mode Register
#define AT91C_APMC_SCER ((AT91_REG *) 0xFFFF4000) // (APMC) System Clock Enable Register
#define AT91C_APMC_SCSR ((AT91_REG *) 0xFFFF4008) // (APMC) System Clock Status Register
#define AT91C_APMC_PCER ((AT91_REG *) 0xFFFF4010) // (APMC) Peripheral Clock Enable Register
#define AT91C_APMC_SCDR ((AT91_REG *) 0xFFFF4004) // (APMC) System Clock Disable Register
#define AT91C_APMC_PCDR ((AT91_REG *) 0xFFFF4014) // (APMC) Peripheral Clock Disable Register
#define AT91C_APMC_IDR ((AT91_REG *) 0xFFFF4038) // (APMC) Interrupt Disable Register
// ========== Register definition for RTC peripheral ==========
#define AT91C_RTC_IMR ((AT91_REG *) 0xFFFB8028) // (RTC) Interrupt Mask Register
#define AT91C_RTC_IER ((AT91_REG *) 0xFFFB8020) // (RTC) Interrupt Enable Register
#define AT91C_RTC_SR ((AT91_REG *) 0xFFFB8018) // (RTC) Status Register
#define AT91C_RTC_TAR ((AT91_REG *) 0xFFFB8010) // (RTC) Time Alarm Register
#define AT91C_RTC_TIMR ((AT91_REG *) 0xFFFB8008) // (RTC) Time Register
#define AT91C_RTC_MR ((AT91_REG *) 0xFFFB8000) // (RTC) Mode Register
#define AT91C_RTC_VER ((AT91_REG *) 0xFFFB802C) // (RTC) Valid Entry Register
#define AT91C_RTC_IDR ((AT91_REG *) 0xFFFB8024) // (RTC) Interrupt Disable Register
#define AT91C_RTC_SCR ((AT91_REG *) 0xFFFB801C) // (RTC) Status Clear Register
#define AT91C_RTC_CAR ((AT91_REG *) 0xFFFB8014) // (RTC) Calendar Alarm Register
#define AT91C_RTC_CALR ((AT91_REG *) 0xFFFB800C) // (RTC) Calendar Register
#define AT91C_RTC_HMR ((AT91_REG *) 0xFFFB8004) // (RTC) Hour Mode Register
// ========== Register definition for PIOB peripheral ==========
#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFF0058) // (PIOB) Multi-driver Status Register
#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFF0028) // (PIOB) Input Filter Status Register
#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFF0020) // (PIOB) Input Filter Enable Register
#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFF0018) // (PIOB) Output Status Register
#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFF0010) // (PIOB) Output Enable Register
#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFF0008) // (PIOB) PIO Status Register
#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFF003C) // (PIOB) Pin Data Status Register
#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFF0034) // (PIOB) Clear Output Data Register
#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFF0024) // (PIOB) Input Filter Disable Register
#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFF0050) // (PIOB) Multi-driver Enable Register
#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFF0048) // (PIOB) Interrupt Mask Register
#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFF0040) // (PIOB) Interrupt Enable Register
#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFF0038) // (PIOB) Output Data Status Register
#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFF0030) // (PIOB) Set Output Data Register
#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFF0000) // (PIOB) PIO Enable Register
#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFF0054) // (PIOB) Multi-driver Disable Register
#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFF004C) // (PIOB) Interrupt Status Register
#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFF0044) // (PIOB) Interrupt Disable Register
#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFF0004) // (PIOB) PIO Disable Register
#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFF0014) // (PIOB) Output Disable Registerr
// ========== Register definition for PIOA peripheral ==========
#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFEC054) // (PIOA) Multi-driver Disable Register
#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFEC04C) // (PIOA) Interrupt Status Register
#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFEC044) // (PIOA) Interrupt Disable Register
#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFEC03C) // (PIOA) Pin Data Status Register
#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFEC034) // (PIOA) Clear Output Data Register
#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFEC004) // (PIOA) PIO Disable Register
#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFEC058) // (PIOA) Multi-driver Statu⌨️ 快捷键说明
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