📄 at91m55800a.h
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#define AT91C_APMC_WKACKS_OUT_TRIS ((unsigned int) 0x0 << 2) // (APMC) Tri-stated
#define AT91C_APMC_WKACKS_OUT_LEVEL0 ((unsigned int) 0x1 << 2) // (APMC) Level 0
#define AT91C_APMC_WKACKS_OUT_LEVEL1 ((unsigned int) 0x2 << 2) // (APMC) Level 1
#define AT91C_APMC_ALWKEN ((unsigned int) 0x1 << 4) // (APMC) Alarm Wake-up Enable
#define AT91C_APMC_WKEDG ((unsigned int) 0x3 << 6) // (APMC) Wake-up Input Edge Selection
#define AT91C_APMC_WKEDG_NONE ((unsigned int) 0x0 << 6) // (APMC) None. No edge is detected on wake-up
#define AT91C_APMC_WKEDG_POS_EDG ((unsigned int) 0x1 << 6) // (APMC) Positive edge
#define AT91C_APMC_WKEDG_NEG_EDG ((unsigned int) 0x2 << 6) // (APMC) Negative edge
#define AT91C_APMC_WKEDG_BOTH_EDG ((unsigned int) 0x3 << 6) // (APMC) Both edges
// -------- APMC_SR : (APMC Offset: 0x30) APMC Status Register --------
#define AT91C_APMC_MOSCS ((unsigned int) 0x1 << 0) // (APMC) Main Oscillator Status
#define AT91C_APMC_LOCK ((unsigned int) 0x1 << 1) // (APMC) PLL Lock Status
// -------- APMC_IER : (APMC Offset: 0x34) APMC Interrupt Enable Register --------
// -------- APMC_IDR : (APMC Offset: 0x38) APMC Interrupt Disable Register --------
// -------- APMC_IMR : (APMC Offset: 0x3c) APMC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Real-time Clock Alarm
// *****************************************************************************
typedef struct _AT91S_RTC {
AT91_REG RTC_MR; // Mode Register
AT91_REG RTC_HMR; // Hour Mode Register
AT91_REG RTC_TIMR; // Time Register
AT91_REG RTC_CALR; // Calendar Register
AT91_REG RTC_TAR; // Time Alarm Register
AT91_REG RTC_CAR; // Calendar Alarm Register
AT91_REG RTC_SR; // Status Register
AT91_REG RTC_SCR; // Status Clear Register
AT91_REG RTC_IER; // Interrupt Enable Register
AT91_REG RTC_IDR; // Interrupt Disable Register
AT91_REG RTC_IMR; // Interrupt Mask Register
AT91_REG RTC_VER; // Valid Entry Register
} AT91S_RTC, *AT91PS_RTC;
// -------- RTC_MR : (RTC Offset: 0x0) RTC Mode Register --------
#define AT91C_RTC_UPDTIM ((unsigned int) 0x1 << 0) // (RTC) Update Request Time Register
#define AT91C_RTC_UPDCAL ((unsigned int) 0x1 << 1) // (RTC) Update Request Calendar Register
#define AT91C_RTC_TEVSEL ((unsigned int) 0x3 << 8) // (RTC) Time Event Selection
#define AT91C_RTC_TEVSEL_MN_CHG ((unsigned int) 0x0 << 8) // (RTC) Minute change.
#define AT91C_RTC_TEVSEL_HR_CHG ((unsigned int) 0x1 << 8) // (RTC) Hour change.
#define AT91C_RTC_TEVSEL_EVDAY_MD ((unsigned int) 0x2 << 8) // (RTC) Every day at midnight.
#define AT91C_RTC_TEVSEL_EVDAY_NOON ((unsigned int) 0x3 << 8) // (RTC) Every day at noon.
#define AT91C_RTC_CEVSEL ((unsigned int) 0x3 << 16) // (RTC) Calendar Event Selection
#define AT91C_RTC_CEVSEL_WEEK_CHG ((unsigned int) 0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00).
#define AT91C_RTC_CEVSEL_MONTH_CHG ((unsigned int) 0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).
#define AT91C_RTC_CEVSEL_YEAR_CHG ((unsigned int) 0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00).
// -------- RTC_HMR : (RTC Offset: 0x4) RTC Hour Mode Register --------
#define AT91C_RTC_HRMOD ((unsigned int) 0x1 << 0) // (RTC) 12-24 hour Mode
// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register --------
#define AT91C_RTC_SEC ((unsigned int) 0x7F << 0) // (RTC) Current Second
#define AT91C_RTC_MIN ((unsigned int) 0x7F << 8) // (RTC) Current Minute
#define AT91C_RTC_HOUR ((unsigned int) 0x3F << 16) // (RTC) Current Hour
#define AT91C_RTC_AMPM ((unsigned int) 0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator
// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register --------
#define AT91C_RTC_CENT ((unsigned int) 0x3F << 0) // (RTC) Current Century
#define AT91C_RTC_YEAR ((unsigned int) 0xFF << 8) // (RTC) Current Year
#define AT91C_RTC_MONTH ((unsigned int) 0x1F << 16) // (RTC) Current Month
#define AT91C_RTC_DAY ((unsigned int) 0x7 << 21) // (RTC) Current Day
#define AT91C_RTC_DATE ((unsigned int) 0x3F << 24) // (RTC) Current Date
// -------- RTC_TAR : (RTC Offset: 0x10) RTC Time Alarm Register --------
#define AT91C_RTC_SECEN ((unsigned int) 0x1 << 7) // (RTC) Second Alarm Enable
#define AT91C_RTC_MINEN ((unsigned int) 0x1 << 15) // (RTC) Minute Alarm
#define AT91C_RTC_HOUREN ((unsigned int) 0x1 << 23) // (RTC) Current Hour
// -------- RTC_CAR : (RTC Offset: 0x14) RTC Calendar Alarm Register --------
#define AT91C_RTC_MTHEN ((unsigned int) 0x1 << 23) // (RTC) Month Alarm Enable
#define AT91C_RTC_DATEN ((unsigned int) 0x1 << 31) // (RTC) Date Alarm Enable
// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register --------
#define AT91C_RTC_ACKUPD ((unsigned int) 0x1 << 0) // (RTC) Acknowledge for Update
#define AT91C_RTC_ALARM ((unsigned int) 0x1 << 1) // (RTC) Alarm Flag
#define AT91C_RTC_SECEV ((unsigned int) 0x1 << 2) // (RTC) Second Event
#define AT91C_RTC_TIMEV ((unsigned int) 0x1 << 3) // (RTC) Time Event
#define AT91C_RTC_CALEV ((unsigned int) 0x1 << 4) // (RTC) Calendar event
// -------- RTC_SCR : (RTC Offset: 0x1c) RTC Status Clear Register --------
// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register --------
// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register --------
// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register --------
// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register --------
#define AT91C_RTC_NVT ((unsigned int) 0x1 << 0) // (RTC) Non valid Time
#define AT91C_RTC_NVC ((unsigned int) 0x1 << 1) // (RTC) Non valid Calendar
#define AT91C_RTC_NVTAL ((unsigned int) 0x1 << 2) // (RTC) Non valid time Alarm
#define AT91C_RTC_NVCAL ((unsigned int) 0x1 << 3) // (RTC) Nonvalid Calendar Alarm
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
typedef struct _AT91S_PIO {
AT91_REG PIO_PER; // PIO Enable Register
AT91_REG PIO_PDR; // PIO Disable Register
AT91_REG PIO_PSR; // PIO Status Register
AT91_REG Reserved0[1]; //
AT91_REG PIO_OER; // Output Enable Register
AT91_REG PIO_ODR; // Output Disable Registerr
AT91_REG PIO_OSR; // Output Status Register
AT91_REG Reserved1[1]; //
AT91_REG PIO_IFER; // Input Filter Enable Register
AT91_REG PIO_IFDR; // Input Filter Disable Register
AT91_REG PIO_IFSR; // Input Filter Status Register
AT91_REG Reserved2[1]; //
AT91_REG PIO_SODR; // Set Output Data Register
AT91_REG PIO_CODR; // Clear Output Data Register
AT91_REG PIO_ODSR; // Output Data Status Register
AT91_REG PIO_PDSR; // Pin Data Status Register
AT91_REG PIO_IER; // Interrupt Enable Register
AT91_REG PIO_IDR; // Interrupt Disable Register
AT91_REG PIO_IMR; // Interrupt Mask Register
AT91_REG PIO_ISR; // Interrupt Status Register
AT91_REG PIO_MDER; // Multi-driver Enable Register
AT91_REG PIO_MDDR; // Multi-driver Disable Register
AT91_REG PIO_MDSR; // Multi-driver Status Register
} AT91S_PIO, *AT91PS_PIO;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
// *****************************************************************************
typedef struct _AT91S_TC {
AT91_REG TC_CCR; // Channel Control Register
AT91_REG TC_CMR; // Channel Mode Register
AT91_REG Reserved0[2]; //
AT91_REG TC_CV; // Counter Value
AT91_REG TC_RA; // Register A
AT91_REG TC_RB; // Register B
AT91_REG TC_RC; // Register C
AT91_REG TC_SR; // Status Register
AT91_REG TC_IER; // Interrupt Enable Register
AT91_REG TC_IDR; // Interrupt Disable Register
AT91_REG TC_IMR; // Interrupt Mask Register
} AT91S_TC, *AT91PS_TC;
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x1 << 13) // (TC) UP mode with automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x2 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
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