📄 at91m55800a.h
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// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// The software is delivered "AS IS" without warranty or condition of any
// kind, either express, implied or statutory. This includes without
// limitation any warranty or condition with respect to merchantability or
// fitness for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ----------------------------------------------------------------------------
// File Name : AT91M55800A.h
// Object : AT91M55800A definitions
// Generated : AT91 SW Application Group 07/01/2003 (17:21:53)
//
// CVS Reference : /AT91M55800A.pl/1.18/Thu Nov 21 12:37:56 2002//
// CVS Reference : /AIC_1246F.pl/1.4/Mon Nov 04 16:50:58 2002//
// CVS Reference : /WD_1241B.pl/1.1/Mon Nov 04 16:51:00 2002//
// CVS Reference : /APMC_55800A.pl/1.1/Thu Nov 21 12:37:30 2002//
// CVS Reference : /RTC_1366C.pl/1.2/Mon Nov 04 16:50:58 2002//
// CVS Reference : /PIO_1321C.pl/1.5/Tue Oct 29 14:50:24 2002//
// CVS Reference : /TC_1243B.pl/1.4/Tue Nov 05 11:43:10 2002//
// CVS Reference : /PDC_1363D.pl/1.3/Wed Oct 23 13:49:46 2002//
// CVS Reference : /US_1242E.pl/1.5/Thu Nov 21 12:37:56 2002//
// CVS Reference : /SPI_1244C.pl/1.5/Tue Nov 05 16:13:46 2002//
// CVS Reference : /ADC_55800A.pl/1.3/Tue Nov 05 16:02:02 2002//
// CVS Reference : /DAC_55800A.pl/1.1/Tue Nov 05 11:43:10 2002//
// CVS Reference : /SF_M55800A.pl/1.1/Tue Nov 05 14:45:40 2002//
// CVS Reference : /EBI_55800A.pl/1.3/Wed Feb 19 08:25:20 2003//
// ----------------------------------------------------------------------------
#ifndef AT91M55800A_H
#define AT91M55800A_H
typedef volatile unsigned int AT91_REG;// Hardware register definition
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
typedef struct _AT91S_AIC {
AT91_REG AIC_SMR[32]; // Source Mode egister
AT91_REG AIC_SVR[32]; // Source Vector egister
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command egister
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
} AT91S_AIC, *AT91PS_AIC;
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Interface
// *****************************************************************************
typedef struct _AT91S_WD {
AT91_REG WD_OMR; // Overflow Mode Register
AT91_REG WD_CMR; // Clock Mode Register
AT91_REG WD_CR; // Control Register
AT91_REG WD_SR; // Status Register
} AT91S_WD, *AT91PS_WD;
// -------- WD_OMR : (WD Offset: 0x0) Overflow Mode Register --------
#define AT91C_WD_WDEN ((unsigned int) 0x1 << 0) // (WD) Watchdog Enable
#define AT91C_WD_RSTEN ((unsigned int) 0x1 << 1) // (WD) Reset Enable
#define AT91C_WD_IRQEN ((unsigned int) 0x1 << 2) // (WD) Interrupt Enable
#define AT91C_WD_EXTEN ((unsigned int) 0x1 << 3) // (WD) External Signal Enable
#define AT91C_WD_OKEY ((unsigned int) 0xFFF << 4) // (WD) Watchdog Enable
// -------- WD_CMR : (WD Offset: 0x4) Clock Mode Register --------
#define AT91C_WD_WDCLKS ((unsigned int) 0x3 << 0) // (WD) Clock Selection
#define AT91C_WD_WDCLKS_MCK32 ((unsigned int) 0x0) // (WD) Master Clock divided by 32
#define AT91C_WD_WDCLKS_MCK128 ((unsigned int) 0x1) // (WD) Master Clock divided by 128
#define AT91C_WD_WDCLKS_MCK1024 ((unsigned int) 0x2) // (WD) Master Clock divided by 1024
#define AT91C_WD_WDCLKS_MCK4096 ((unsigned int) 0x3) // (WD) Master Clock divided by 4096
#define AT91C_WD_HPCV ((unsigned int) 0xF << 2) // (WD) High Pre-load Counter Value
#define AT91C_WD_CKEY ((unsigned int) 0x1FF << 7) // (WD) Clock Access Key
// -------- WD_CR : (WD Offset: 0x8) Control Register --------
#define AT91C_WD_RSTKEY ((unsigned int) 0xFFFF << 0) // (WD) Restart Key
// -------- WD_SR : (WD Offset: 0xc) Status Register --------
#define AT91C_WD_WDOVF ((unsigned int) 0x1 << 0) // (WD) Watchdog Overflow
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Power Management Controler
// *****************************************************************************
typedef struct _AT91S_APMC {
AT91_REG APMC_SCER; // System Clock Enable Register
AT91_REG APMC_SCDR; // System Clock Disable Register
AT91_REG APMC_SCSR; // System Clock Status Register
AT91_REG Reserved0[1]; //
AT91_REG APMC_PCER; // Peripheral Clock Enable Register
AT91_REG APMC_PCDR; // Peripheral Clock Disable Register
AT91_REG APMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved1[1]; //
AT91_REG APMC_CGMR; // Clock Generator Mode Register
AT91_REG Reserved2[1]; //
AT91_REG APMC_PCR; // Power Control Register
AT91_REG APMC_PMR; // Power Mode Register
AT91_REG APMC_SR; // Status Register
AT91_REG APMC_IER; // Interrupt Enable Register
AT91_REG APMC_IDR; // Interrupt Disable Register
AT91_REG APMC_IMR; // Interrupt Mask Register
} AT91S_APMC, *AT91PS_APMC;
// -------- APMC_SCER : (APMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_APMC_CPU ((unsigned int) 0x1 << 0) // (APMC) System Clock
// -------- APMC_SCDR : (APMC Offset: 0x4) System Clock Disable Register --------
// -------- APMC_SCSR : (APMC Offset: 0x8) System Clock Status Register --------
// -------- APMC_PCER : (APMC Offset: 0x10) Peripheral Clock Enable Register --------
#define AT91C_APMC_US0 ((unsigned int) 0x1 << 2) // (APMC) Usart 0 Clock
#define AT91C_APMC_US1 ((unsigned int) 0x1 << 3) // (APMC) Usart 1 Clock
#define AT91C_APMC_US2 ((unsigned int) 0x1 << 4) // (APMC) Usart 2 Clock
#define AT91C_APMC_SPI ((unsigned int) 0x1 << 5) // (APMC) Serial Peripheral Interface Clock
#define AT91C_APMC_TC0 ((unsigned int) 0x1 << 6) // (APMC) Timer Counter 0 Clock
#define AT91C_APMC_TC1 ((unsigned int) 0x1 << 7) // (APMC) Timer Counter 1 Clock
#define AT91C_APMC_TC2 ((unsigned int) 0x1 << 8) // (APMC) Timer Counter 2 Clock
#define AT91C_APMC_TC3 ((unsigned int) 0x1 << 9) // (APMC) Timer Counter 3 Clock
#define AT91C_APMC_TC4 ((unsigned int) 0x1 << 10) // (APMC) Timer Counter 4 Clock
#define AT91C_APMC_TC5 ((unsigned int) 0x1 << 11) // (APMC) Timer Counter 5 Clock
#define AT91C_APMC_PIOA ((unsigned int) 0x1 << 13) // (APMC) PIOA Clock
#define AT91C_APMC_PIOB ((unsigned int) 0x1 << 14) // (APMC) PIOB Clock
#define AT91C_APMC_ADC0 ((unsigned int) 0x1 << 15) // (APMC) Analog to Digital Converter 0 Clock
#define AT91C_APMC_ADC1 ((unsigned int) 0x1 << 16) // (APMC) Analog to Digital Converter 1 Clock
#define AT91C_APMC_DAC0 ((unsigned int) 0x1 << 17) // (APMC) Digital to Analog Converter 0 Clock
#define AT91C_APMC_DAC1 ((unsigned int) 0x1 << 18) // (APMC) Digital to Analog Converter 1 Clock
// -------- APMC_PCDR : (APMC Offset: 0x14) Peripheral Clock Disable Register --------
// -------- APMC_PCSR : (APMC Offset: 0x18) Peripheral Clock Satus Register --------
// -------- APMC_CGMR : (APMC Offset: 0x20) Clock Generator Mode Register --------
#define AT91C_APMC_MOSCBYP ((unsigned int) 0x1 << 0) // (APMC) Main Oscillator Bypass
#define AT91C_APMC_MOSCEN ((unsigned int) 0x1 << 1) // (APMC) Main Oscillator Enable
#define AT91C_APMC_MCKODS ((unsigned int) 0x1 << 2) // (APMC) Master Clock Output Disable
#define AT91C_APMC_PRES ((unsigned int) 0x7 << 4) // (APMC) Prescaler Selection
#define AT91C_APMC_PRES_NONE ((unsigned int) 0x0 << 4) // (APMC) Prescaler Output is the selected clock
#define AT91C_APMC_PRES_DIV2 ((unsigned int) 0x1 << 4) // (APMC) Selected clock is divided by 2
#define AT91C_APMC_PRES_DIV4 ((unsigned int) 0x2 << 4) // (APMC) Selected clock is divided by 4
#define AT91C_APMC_PRES_DIV8 ((unsigned int) 0x3 << 4) // (APMC) Selected clock is divided by 8
#define AT91C_APMC_PRES_DIV16 ((unsigned int) 0x4 << 4) // (APMC) Selected clock is divided by 16
#define AT91C_APMC_PRES_DIV32 ((unsigned int) 0x5 << 4) // (APMC) Selected clock is divided by 32
#define AT91C_APMC_PRES_DIV64 ((unsigned int) 0x6 << 4) // (APMC) Selected clock is divided by 64
#define AT91C_APMC_MUL ((unsigned int) 0x3F << 8) // (APMC) Phase Lock Loop Factor
#define AT91C_APMC_CSS ((unsigned int) 0x3 << 14) // (APMC) Clock Source Selection
#define AT91C_APMC_CSS_LF ((unsigned int) 0x0 << 14) // (APMC) Low-frequency clock provided by the RTC
#define AT91C_APMC_CSS_MOSC ((unsigned int) 0x1 << 14) // (APMC) Main Oscillator Output or external clock
#define AT91C_APMC_CSS_PLL ((unsigned int) 0x2 << 14) // (APMC) Phase Locked Loop Output
#define AT91C_APMC_OSCOUNT ((unsigned int) 0x3F << 16) // (APMC) Main Oscillator Counter
#define AT91C_APMC_PLLCOUNT ((unsigned int) 0x1 << 24) // (APMC) PLL Lock Counter
// -------- APMC_PCR : (APMC Offset: 0x28) Power Control Register --------
#define AT91C_APMC_SHDALC ((unsigned int) 0x1 << 0) // (APMC) Shut-down or Alarm Command
#define AT91C_APMC_WKACKC ((unsigned int) 0x1 << 1) // (APMC) Wake-up or Alarm Acknoledge Command
// -------- APMC_PMR : (APMC Offset: 0x2c) Power Mode Register --------
#define AT91C_APMC_SHDALS ((unsigned int) 0x3 << 0) // (APMC) Shut-down or Alarm Command
#define AT91C_APMC_SHDALS_OUT_TRIS ((unsigned int) 0x0) // (APMC) Tri-stated
#define AT91C_APMC_SHDALS_OUT_LEVEL0 ((unsigned int) 0x1) // (APMC) Level 0
#define AT91C_APMC_SHDALS_OUT_LEVEL1 ((unsigned int) 0x2) // (APMC) Level 1
#define AT91C_APMC_WKACKS ((unsigned int) 0x1 << 2) // (APMC) Wake-up or Alarm Acknoledge Command
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