at91m55800a.inc

前段时间做了一个AT91M55800的芯片测试

AT91C_APMC_PCR            EQU (0xFFFF4028) ;- (APMC) Power Control Register
AT91C_APMC_CGMR           EQU (0xFFFF4020) ;- (APMC) Clock Generator Mode Register
AT91C_APMC_PCSR           EQU (0xFFFF4018) ;- (APMC) Peripheral Clock Status Register
AT91C_APMC_IMR            EQU (0xFFFF403C) ;- (APMC) Interrupt Mask Register
AT91C_APMC_IER            EQU (0xFFFF4034) ;- (APMC) Interrupt Enable Register
AT91C_APMC_PMR            EQU (0xFFFF402C) ;- (APMC) Power Mode Register
AT91C_APMC_SCER           EQU (0xFFFF4000) ;- (APMC) System Clock Enable Register
AT91C_APMC_SCSR           EQU (0xFFFF4008) ;- (APMC) System Clock Status Register
AT91C_APMC_PCER           EQU (0xFFFF4010) ;- (APMC) Peripheral Clock Enable Register
AT91C_APMC_SCDR           EQU (0xFFFF4004) ;- (APMC) System Clock Disable Register
AT91C_APMC_PCDR           EQU (0xFFFF4014) ;- (APMC) Peripheral Clock Disable Register
AT91C_APMC_IDR            EQU (0xFFFF4038) ;- (APMC) Interrupt Disable Register
;- ========== Register definition for RTC peripheral ========== 
AT91C_RTC_IMR             EQU (0xFFFB8028) ;- (RTC) Interrupt Mask Register
AT91C_RTC_IER             EQU (0xFFFB8020) ;- (RTC) Interrupt Enable Register
AT91C_RTC_SR              EQU (0xFFFB8018) ;- (RTC) Status Register
AT91C_RTC_TAR             EQU (0xFFFB8010) ;- (RTC) Time Alarm Register
AT91C_RTC_TIMR            EQU (0xFFFB8008) ;- (RTC) Time Register
AT91C_RTC_MR              EQU (0xFFFB8000) ;- (RTC) Mode Register
AT91C_RTC_VER             EQU (0xFFFB802C) ;- (RTC) Valid Entry Register
AT91C_RTC_IDR             EQU (0xFFFB8024) ;- (RTC) Interrupt Disable Register
AT91C_RTC_SCR             EQU (0xFFFB801C) ;- (RTC) Status Clear Register
AT91C_RTC_CAR             EQU (0xFFFB8014) ;- (RTC) Calendar Alarm Register
AT91C_RTC_CALR            EQU (0xFFFB800C) ;- (RTC) Calendar Register
AT91C_RTC_HMR             EQU (0xFFFB8004) ;- (RTC) Hour Mode Register
;- ========== Register definition for PIOB peripheral ========== 
AT91C_PIOB_MDSR           EQU (0xFFFF0058) ;- (PIOB) Multi-driver Status Register
AT91C_PIOB_IFSR           EQU (0xFFFF0028) ;- (PIOB) Input Filter Status Register
AT91C_PIOB_IFER           EQU (0xFFFF0020) ;- (PIOB) Input Filter Enable Register
AT91C_PIOB_OSR            EQU (0xFFFF0018) ;- (PIOB) Output Status Register
AT91C_PIOB_OER            EQU (0xFFFF0010) ;- (PIOB) Output Enable Register
AT91C_PIOB_PSR            EQU (0xFFFF0008) ;- (PIOB) PIO Status Register
AT91C_PIOB_PDSR           EQU (0xFFFF003C) ;- (PIOB) Pin Data Status Register
AT91C_PIOB_CODR           EQU (0xFFFF0034) ;- (PIOB) Clear Output Data Register
AT91C_PIOB_IFDR           EQU (0xFFFF0024) ;- (PIOB) Input Filter Disable Register
AT91C_PIOB_MDER           EQU (0xFFFF0050) ;- (PIOB) Multi-driver Enable Register
AT91C_PIOB_IMR            EQU (0xFFFF0048) ;- (PIOB) Interrupt Mask Register
AT91C_PIOB_IER            EQU (0xFFFF0040) ;- (PIOB) Interrupt Enable Register
AT91C_PIOB_ODSR           EQU (0xFFFF0038) ;- (PIOB) Output Data Status Register
AT91C_PIOB_SODR           EQU (0xFFFF0030) ;- (PIOB) Set Output Data Register
AT91C_PIOB_PER            EQU (0xFFFF0000) ;- (PIOB) PIO Enable Register
AT91C_PIOB_MDDR           EQU (0xFFFF0054) ;- (PIOB) Multi-driver Disable Register
AT91C_PIOB_ISR            EQU (0xFFFF004C) ;- (PIOB) Interrupt Status Register
AT91C_PIOB_IDR            EQU (0xFFFF0044) ;- (PIOB) Interrupt Disable Register
AT91C_PIOB_PDR            EQU (0xFFFF0004) ;- (PIOB) PIO Disable Register
AT91C_PIOB_ODR            EQU (0xFFFF0014) ;- (PIOB) Output Disable Registerr
;- ========== Register definition for PIOA peripheral ========== 
AT91C_PIOA_MDDR           EQU (0xFFFEC054) ;- (PIOA) Multi-driver Disable Register
AT91C_PIOA_ISR            EQU (0xFFFEC04C) ;- (PIOA) Interrupt Status Register
AT91C_PIOA_IDR            EQU (0xFFFEC044) ;- (PIOA) Interrupt Disable Register
AT91C_PIOA_PDSR           EQU (0xFFFEC03C) ;- (PIOA) Pin Data Status Register
AT91C_PIOA_CODR           EQU (0xFFFEC034) ;- (PIOA) Clear Output Data Register
AT91C_PIOA_PDR            EQU (0xFFFEC004) ;- (PIOA) PIO Disable Register
AT91C_PIOA_MDSR           EQU (0xFFFEC058) ;- (PIOA) Multi-driver Status Register
AT91C_PIOA_MDER           EQU (0xFFFEC050) ;- (PIOA) Multi-driver Enable Register
AT91C_PIOA_IMR            EQU (0xFFFEC048) ;- (PIOA) Interrupt Mask Register
AT91C_PIOA_OSR            EQU (0xFFFEC018) ;- (PIOA) Output Status Register
AT91C_PIOA_OER            EQU (0xFFFEC010) ;- (PIOA) Output Enable Register
AT91C_PIOA_PSR            EQU (0xFFFEC008) ;- (PIOA) PIO Status Register
AT91C_PIOA_PER            EQU (0xFFFEC000) ;- (PIOA) PIO Enable Register
AT91C_PIOA_IFDR           EQU (0xFFFEC024) ;- (PIOA) Input Filter Disable Register
AT91C_PIOA_ODR            EQU (0xFFFEC014) ;- (PIOA) Output Disable Registerr
AT91C_PIOA_IER            EQU (0xFFFEC040) ;- (PIOA) Interrupt Enable Register
AT91C_PIOA_ODSR           EQU (0xFFFEC038) ;- (PIOA) Output Data Status Register
AT91C_PIOA_SODR           EQU (0xFFFEC030) ;- (PIOA) Set Output Data Register
AT91C_PIOA_IFSR           EQU (0xFFFEC028) ;- (PIOA) Input Filter Status Register
AT91C_PIOA_IFER           EQU (0xFFFEC020) ;- (PIOA) Input Filter Enable Register
;- ========== Register definition for TC5 peripheral ========== 
AT91C_TC5_IDR             EQU (0xFFFD40A8) ;- (TC5) Interrupt Disable Register
AT91C_TC5_SR              EQU (0xFFFD40A0) ;- (TC5) Status Register
AT91C_TC5_RB              EQU (0xFFFD4098) ;- (TC5) Register B
AT91C_TC5_CV              EQU (0xFFFD4090) ;- (TC5) Counter Value
AT91C_TC5_CCR             EQU (0xFFFD4080) ;- (TC5) Channel Control Register
AT91C_TC5_IMR             EQU (0xFFFD40AC) ;- (TC5) Interrupt Mask Register
AT91C_TC5_IER             EQU (0xFFFD40A4) ;- (TC5) Interrupt Enable Register
AT91C_TC5_RC              EQU (0xFFFD409C) ;- (TC5) Register C
AT91C_TC5_RA              EQU (0xFFFD4094) ;- (TC5) Register A
AT91C_TC5_CMR             EQU (0xFFFD4084) ;- (TC5) Channel Mode Register
;- ========== Register definition for TC4 peripheral ========== 
AT91C_TC4_IDR             EQU (0xFFFD4068) ;- (TC4) Interrupt Disable Register
AT91C_TC4_SR              EQU (0xFFFD4060) ;- (TC4) Status Register
AT91C_TC4_RB              EQU (0xFFFD4058) ;- (TC4) Register B
AT91C_TC4_CV              EQU (0xFFFD4050) ;- (TC4) Counter Value
AT91C_TC4_CCR             EQU (0xFFFD4040) ;- (TC4) Channel Control Register
AT91C_TC4_IMR             EQU (0xFFFD406C) ;- (TC4) Interrupt Mask Register
AT91C_TC4_IER             EQU (0xFFFD4064) ;- (TC4) Interrupt Enable Register
AT91C_TC4_RC              EQU (0xFFFD405C) ;- (TC4) Register C
AT91C_TC4_RA              EQU (0xFFFD4054) ;- (TC4) Register A
AT91C_TC4_CMR             EQU (0xFFFD4044) ;- (TC4) Channel Mode Register
;- ========== Register definition for TC3 peripheral ========== 
AT91C_TC3_RA              EQU (0xFFFD4014) ;- (TC3) Register A
AT91C_TC3_CMR             EQU (0xFFFD4004) ;- (TC3) Channel Mode Register
AT91C_TC3_IDR             EQU (0xFFFD4028) ;- (TC3) Interrupt Disable Register
AT91C_TC3_SR              EQU (0xFFFD4020) ;- (TC3) Status Register
AT91C_TC3_RB              EQU (0xFFFD4018) ;- (TC3) Register B
AT91C_TC3_CV              EQU (0xFFFD4010) ;- (TC3) Counter Value
AT91C_TC3_CCR             EQU (0xFFFD4000) ;- (TC3) Channel Control Register
AT91C_TC3_IMR             EQU (0xFFFD402C) ;- (TC3) Interrupt Mask Register
AT91C_TC3_IER             EQU (0xFFFD4024) ;- (TC3) Interrupt Enable Register
AT91C_TC3_RC              EQU (0xFFFD401C) ;- (TC3) Register C
;- ========== Register definition for TCB1 peripheral ========== 
AT91C_TCB1_BCR            EQU (0xFFFD40C0) ;- (TCB1) TC Block Control Register
AT91C_TCB1_BMR            EQU (0xFFFD40C4) ;- (TCB1) TC Block Mode Register
;- ========== Register definition for TC2 peripheral ========== 
AT91C_TC2_IDR             EQU (0xFFFD00A8) ;- (TC2) Interrupt Disable Register
AT91C_TC2_SR              EQU (0xFFFD00A0) ;- (TC2) Status Register
AT91C_TC2_RB              EQU (0xFFFD0098) ;- (TC2) Register B
AT91C_TC2_CV              EQU (0xFFFD0090) ;- (TC2) Counter Value
AT91C_TC2_CCR             EQU (0xFFFD0080) ;- (TC2) Channel Control Register
AT91C_TC2_IMR             EQU (0xFFFD00AC) ;- (TC2) Interrupt Mask Register
AT91C_TC2_IER             EQU (0xFFFD00A4) ;- (TC2) Interrupt Enable Register
AT91C_TC2_RC              EQU (0xFFFD009C) ;- (TC2) Register C
AT91C_TC2_RA              EQU (0xFFFD0094) ;- (TC2) Register A
AT91C_TC2_CMR             EQU (0xFFFD0084) ;- (TC2) Channel Mode Register
;- ========== Register definition for TC1 peripheral ========== 
AT91C_TC1_IMR             EQU (0xFFFD006C) ;- (TC1) Interrupt Mask Register
AT91C_TC1_IER             EQU (0xFFFD0064) ;- (TC1) Interrupt Enable Register
AT91C_TC1_RC              EQU (0xFFFD005C) ;- (TC1) Register C
AT91C_TC1_RA              EQU (0xFFFD0054) ;- (TC1) Register A
AT91C_TC1_CMR             EQU (0xFFFD0044) ;- (TC1) Channel Mode Register
AT91C_TC1_IDR             EQU (0xFFFD0068) ;- (TC1) Interrupt Disable Register
AT91C_TC1_SR              EQU (0xFFFD0060) ;- (TC1) Status Register
AT91C_TC1_RB              EQU (0xFFFD0058) ;- (TC1) Register B
AT91C_TC1_CV              EQU (0xFFFD0050) ;- (TC1) Counter Value
AT91C_TC1_CCR             EQU (0xFFFD0040) ;- (TC1) Channel Control Register
;- ========== Register definition for TC0 peripheral ========== 
AT91C_TC0_IMR             EQU (0xFFFD002C) ;- (TC0) Interrupt Mask Register
AT91C_TC0_IER             EQU (0xFFFD0024) ;- (TC0) Interrupt Enable Register
AT91C_TC0_RC              EQU (0xFFFD001C) ;- (TC0) Register C
AT91C_TC0_RA              EQU (0xFFFD0014) ;- (TC0) Register A
AT91C_TC0_CMR             EQU (0xFFFD0004) ;- (TC0) Channel Mode Register
AT91C_TC0_IDR             EQU (0xFFFD0028) ;- (TC0) Interrupt Disable Register
AT91C_TC0_SR              EQU (0xFFFD0020) ;- (TC0) Status Register
AT91C_TC0_RB              EQU (0xFFFD0018) ;- (TC0) Register B
AT91C_TC0_CV              EQU (0xFFFD0010) ;- (TC0) Counter Value
AT91C_TC0_CCR             EQU (0xFFFD0000) ;- (TC0) Channel Control Register
;- ========== Register definition for TCB0 peripheral ========== 
AT91C_TCB0_BCR            EQU (0xFFFD00C0) ;- (TCB0) TC Block Control Register
AT91C_TCB0_BMR            EQU (0xFFFD00C4) ;- (TCB0) TC Block Mode Register
;- ========== Register definition for PDC_US2 peripheral ========== 
AT91C_US2_TPR             EQU (0xFFFC8038) ;- (PDC_US2) Transmit Pointer Register
AT91C_US2_RPR             EQU (0xFFFC8030) ;- (PDC_US2) Receive Pointer Register
AT91C_US2_TCR             EQU (0xFFFC803C) ;- (PDC_US2) Transmit Counter Register
AT91C_US2_RCR             EQU (0xFFFC8034) ;- (PDC_US2) Receive Counter Register
;- ========== Register definition for US2 peripheral ========== 
AT91C_US2_TTGR            EQU (0xFFFC8028) ;- (US2) Transmitter Time-guard Register
AT91C_US2_BRGR            EQU (0xFFFC8020) ;- (US2) Baud Rate Generator Register
AT91C_US2_RHR             EQU (0xFFFC8018) ;- (US2) Receiver Holding Register
AT91C_US2_IMR             EQU (0xFFFC8010) ;- (US2) Interrupt Mask Register
AT91C_US2_IER             EQU (0xFFFC8008) ;- (US2) Interrupt Enable Register
AT91C_US2_CR              EQU (0xFFFC8000) ;- (US2) Control Register
AT91C_US2_RTOR            EQU (0xFFFC8024) ;- (US2) Receiver Time-out Register
AT91C_US2_THR             EQU (0xFFFC801C) ;- (US2) Transmitter Holding Register
AT91C_US2_CSR             EQU (0xFFFC8014) ;- (US2) Channel Status Register
AT91C_US2_IDR             EQU (0xFFFC800C) ;- (US2) Interrupt Disable Register
AT91C_US2_MR              EQU (0xFFFC8004) ;- (US2) Mode Register
;- ========== Register definition for PDC_US1 peripheral ========== 
AT91C_US1_TPR             EQU (0xFFFC4038) ;- (PDC_US1) Transmit Pointer Register
AT91C_US1_RPR             EQU (0xFFFC4030) ;- (PDC_US1) Receive Pointer Register
AT91C_US1_TCR             EQU (0xFFFC403C) ;- (PDC_US1) Transmit Counter Register
AT91C_US1_RCR             EQU (0xFFFC4034) ;- (PDC_US1) Receive Counter Register
;- ========== Register definition for US1 peripheral ========== 
AT91C_US1_TTGR            EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
AT91C_US1_BRGR            EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
AT91C_US1_RHR             EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
AT91C_US1_IMR             EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
AT91C_US1_IER             EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
AT91C_US1_CR              EQU (0xFFFC4000) ;- (US1) Control Register
AT91C_US1_RTOR            EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
AT91C_US1_THR             EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
AT91C_US1_CSR             EQU (0xFFFC4014) ;- (US1) Channel Status Register
AT91C_US1_IDR             EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
AT91C_US1_MR              EQU (0xFFFC4004) ;- (US1) Mode Register
;- ========== Register definition for PDC_US0 peripheral ========== 
AT91C_US0_TPR             EQU (0xFFFC0038) ;- (PDC_US0) Transmit Pointer Register
AT91C_US0_RPR             EQU (0xFFFC0030) ;- (PDC_US0) Receive Pointer Register
AT91C_US0_TCR             EQU (0xFFFC003C) ;- (PDC_US0) Transmit Counter Register
AT91C_US0_RCR             EQU (0xFFFC0034) ;- (PDC_US0) Receive Counter Register
;- ========== Register definition for US0 peripheral ========== 
AT91C_US0_TTGR            EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
AT91C_US0_BRGR            EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
AT91C_US0_RHR             EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
AT91C_US0_IMR             EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
AT91C_US0_IER             EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
AT91C_US0_CR              EQU (0xFFFC0000) ;- (US0) Control Register
AT91C_US0_RTOR            EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
AT91C_US0_THR             EQU (0xFF