📄 at91m55800a.inc
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AT91C_ADC_TRG_TIOA0 EQU (0x0:SHL:1) ;- (ADC) Selected TRGSEL = TIAO0
AT91C_ADC_TRG_TIOA1 EQU (0x1:SHL:1) ;- (ADC) Selected TRGSEL = TIAO1
AT91C_ADC_TRG_TIOA2 EQU (0x2:SHL:1) ;- (ADC) Selected TRGSEL = TIAO2
AT91C_ADC_TRG_TIOA3 EQU (0x3:SHL:1) ;- (ADC) Selected TRGSEL = TIAO3
AT91C_ADC_TRG_TIOA4 EQU (0x4:SHL:1) ;- (ADC) Selected TRGSEL = TIAO4
AT91C_ADC_TRG_TIOA5 EQU (0x5:SHL:1) ;- (ADC) Selected TRGSEL = TIAO5
AT91C_ADC_TRG_EXT EQU (0x6:SHL:1) ;- (ADC) Selected TRGSEL = External Trigger
AT91C_ADC_RES EQU (0x1:SHL:4) ;- (ADC) Resolution.
AT91C_ADC_RES_10_BIT EQU (0x0:SHL:4) ;- (ADC) 10-bit resolution
AT91C_ADC_RES_8_BIT EQU (0x1:SHL:4) ;- (ADC) 8-bit resolution
AT91C_ADC_SLEEP EQU (0x1:SHL:5) ;- (ADC) Sleep Mode
AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0:SHL:5) ;- (ADC) Normal Mode
AT91C_ADC_SLEEP_MODE EQU (0x1:SHL:5) ;- (ADC) Sleep Mode
AT91C_ADC_PRESCAL EQU (0x1F:SHL:8) ;- (ADC) Prescaler rate selection
;- -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register --------
AT91C_ADC_CH0 EQU (0x1:SHL:0) ;- (ADC) Channel 0
AT91C_ADC_CH1 EQU (0x1:SHL:1) ;- (ADC) Channel 1
AT91C_ADC_CH2 EQU (0x1:SHL:2) ;- (ADC) Channel 2
AT91C_ADC_CH3 EQU (0x1:SHL:3) ;- (ADC) Channel 3
;- -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register --------
;- -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register --------
;- -------- ADC_SR : (ADC Offset: 0x20) Status Register --------
AT91C_ADC_EOC0 EQU (0x1:SHL:0) ;- (ADC) End of Conversion
AT91C_ADC_EOC1 EQU (0x1:SHL:1) ;- (ADC) End of Conversion
AT91C_ADC_EOC2 EQU (0x1:SHL:2) ;- (ADC) End of Conversion
AT91C_ADC_EOC3 EQU (0x1:SHL:3) ;- (ADC) End of Conversion
AT91C_ADC_OVRE0 EQU (0x1:SHL:8) ;- (ADC) Overrun Error
AT91C_ADC_OVRE1 EQU (0x1:SHL:9) ;- (ADC) Overrun Error
AT91C_ADC_OVRE2 EQU (0x1:SHL:10) ;- (ADC) Overrun Error
AT91C_ADC_OVRE3 EQU (0x1:SHL:11) ;- (ADC) Overrun Error
;- -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register --------
;- -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register --------
;- -------- ADC_IMR : (ADC Offset: 0x2c) Interrupt Mask Register --------
;- -------- ADC_CDR : (ADC Offset: 0x30) Convert Data Register --------
AT91C_ADC_DATA EQU (0x3FF:SHL:0) ;- (ADC) Converted Data
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Digital to Analog Convertor
;- *****************************************************************************
^ 0 ;- AT91S_DAC
DAC_CR # 4 ;- Control Register
DAC_MR # 4 ;- Mode Register
DAC_DHR # 4 ;- Data Holding Register
DAC_DOR # 4 ;- Data Output Register
DAC_SR # 4 ;- Status Register
DAC_IER # 4 ;- Interrupt Enable Register
DAC_IDR # 4 ;- Interrupt Disable Register
DAC_IMR # 4 ;- Interrupt Mask Register
;- -------- DAC_CR : (DAC Offset: 0x0) Control Register --------
AT91C_DAC_SWRST EQU (0x1:SHL:0) ;- (DAC) Software Reset
;- -------- DAC_MR : (DAC Offset: 0x4) Mode Register --------
AT91C_DAC_TTRGEN EQU (0x1:SHL:0) ;- (DAC) Timer Trigger Enable
AT91C_DAC_TTRGEN_DIS EQU (0x0) ;- (DAC) The data written into the Data Holding Register (DAC_DHR) is transferred one main clock cycle later to the data output register (DAC_DOR).
AT91C_DAC_TTRGEN_EN EQU (0x1) ;- (DAC) The data transfer from the DAC_DHR to the DAC_DOR is synchronized by the timer trigger.
AT91C_DAC_TTRGSEL EQU (0x7:SHL:1) ;- (DAC) Timer Trigger Selection
AT91C_DAC_TTRGSEL_TIOA0 EQU (0x0:SHL:1) ;- (DAC) Selected TRGSEL = TIAO0
AT91C_DAC_TTRGSEL_TIOA1 EQU (0x1:SHL:1) ;- (DAC) Selected TRGSEL = TIAO1
AT91C_DAC_TTRGSEL_TIOA2 EQU (0x2:SHL:1) ;- (DAC) Selected TRGSEL = TIAO2
AT91C_DAC_TTRGSEL_TIOA3 EQU (0x3:SHL:1) ;- (DAC) Selected TRGSEL = TIAO3
AT91C_DAC_TTRGSEL_TIOA4 EQU (0x4:SHL:1) ;- (DAC) Selected TRGSEL = TIAO4
AT91C_DAC_TTRGSEL_TIOA5 EQU (0x5:SHL:1) ;- (DAC) Selected TRGSEL = TIAO5
AT91C_DAC_RES EQU (0x1:SHL:4) ;- (DAC) Resolution.
AT91C_DAC_RES_10_BIT EQU (0x0:SHL:4) ;- (DAC) 10-bit resolution
AT91C_DAC_RES_8_BIT EQU (0x1:SHL:4) ;- (DAC) 8-bit resolution
;- -------- DAC_DHR : (DAC Offset: 0x8) Data Holding Register --------
AT91C_DAC_DATA EQU (0x3FF:SHL:0) ;- (DAC) Data to be Converted
;- -------- DAC_DOR : (DAC Offset: 0xc) Data Output Register --------
;- -------- DAC_SR : (DAC Offset: 0x10) Status Register --------
AT91C_DAC_DATRDY EQU (0x1:SHL:0) ;- (DAC) Data Ready for Conversion
;- -------- DAC_IER : (DAC Offset: 0x14) Data Ready for Conversion Interrupt Enable --------
;- -------- DAC_IDR : (DAC Offset: 0x18) Data Ready for Conversion Interrupt Disable --------
;- -------- DAC_IMR : (DAC Offset: 0x1c) Data Ready for Conversion Interrupt Mask --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Special Function Interface
;- *****************************************************************************
^ 0 ;- AT91S_SF
SF_CIDR # 4 ;- Chip ID Register
SF_EXID # 4 ;- Chip ID Extension Register
SF_RSR # 4 ;- Reset Status Register
# 12 ;- Reserved
SF_PMR # 4 ;- Protect Mode Register
;- -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register --------
AT91C_SF_VERSION EQU (0x1F:SHL:0) ;- (SF) Version of the chip
AT91C_SF_BIT5 EQU (0x1:SHL:5) ;- (SF) Hardwired at 0
AT91C_SF_BIT6 EQU (0x1:SHL:6) ;- (SF) Hardwired at 1
AT91C_SF_BIT7 EQU (0x1:SHL:7) ;- (SF) Hardwired at 0
AT91C_SF_NVPSIZ EQU (0xF:SHL:8) ;- (SF) Nonvolatile Program Memory Size
AT91C_SF_NVPSIZ_NONE EQU (0x0:SHL:8) ;- (SF) None
AT91C_SF_NVPSIZ_32K EQU (0x3:SHL:8) ;- (SF) 32K Bytes
AT91C_SF_NVPSIZ_64K EQU (0x5:SHL:8) ;- (SF) 64K Bytes
AT91C_SF_NVPSIZ_128K EQU (0x7:SHL:8) ;- (SF) 128K Bytes
AT91C_SF_NVPSIZ_256K EQU (0x11:SHL:8) ;- (SF) 256K Bytes
AT91C_SF_NVDSIZ EQU (0xF:SHL:12) ;- (SF) Nonvolatile Data Memory Size
AT91C_SF_NVDSIZ_NONE EQU (0x0:SHL:12) ;- (SF) None
AT91C_SF_VDSIZ EQU (0xF:SHL:16) ;- (SF) Volatile Data Memory Size
AT91C_SF_VDSIZ_NONE EQU (0x0:SHL:16) ;- (SF) None
AT91C_SF_VDSIZ_1K EQU (0x3:SHL:16) ;- (SF) 1K Bytes
AT91C_SF_VDSIZ_2K EQU (0x5:SHL:16) ;- (SF) 2K Bytes
AT91C_SF_VDSIZ_4K EQU (0x7:SHL:16) ;- (SF) 4K Bytes
AT91C_SF_VDSIZ_8K EQU (0x11:SHL:16) ;- (SF) 8K Bytes
AT91C_SF_ARCH EQU (0xFF:SHL:20) ;- (SF) Chip Architecture
AT91C_SF_ARCH_AT91x40 EQU (0x28:SHL:20) ;- (SF) AT91x40yyy
AT91C_SF_ARCH_AT91x55 EQU (0x37:SHL:20) ;- (SF) AT91x55yyy
AT91C_SF_ARCH_AT91x63 EQU (0x3F:SHL:20) ;- (SF) AT91x63yyy
AT91C_SF_NVPTYP EQU (0x7:SHL:28) ;- (SF) Nonvolatile Program Memory Type
AT91C_SF_NVPTYP_NVPTYP_M EQU (0x1:SHL:28) ;- (SF) 'M' Series or 'F' Series
AT91C_SF_NVPTYP_NVPTYP_R EQU (0x4:SHL:28) ;- (SF) 'R' Series
AT91C_SF_EXT EQU (0x1:SHL:31) ;- (SF) Extension Flag
;- -------- SF_RSR : (SF Offset: 0x8) Reset Status Information --------
AT91C_SF_RESET EQU (0xFF:SHL:0) ;- (SF) Cause of Reset
AT91C_SF_RESET_WD EQU (0x35) ;- (SF) Internal Watchdog
AT91C_SF_RESET_EXT EQU (0x6C) ;- (SF) External Pin
;- -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register --------
AT91C_SF_AIC EQU (0x1:SHL:5) ;- (SF) AIC Protect Mode Enable
AT91C_SF_PMRKEY EQU (0xFFFF:SHL:16) ;- (SF) Protect Mode Register Key
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR External Bus Interface
;- *****************************************************************************
^ 0 ;- AT91S_EBI
EBI_CSR # 32 ;- Chip-select Register
EBI_RCR # 4 ;- Remap Control Register
EBI_MCR # 4 ;- Memory Control Register
;- -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register --------
AT91C_EBI_DBW EQU (0x3:SHL:0) ;- (EBI) Data Bus Width
AT91C_EBI_DBW_16 EQU (0x1) ;- (EBI) 16-bit data bus width
AT91C_EBI_DBW_8 EQU (0x2) ;- (EBI) 8-bit data bus width
AT91C_EBI_NWS EQU (0x7:SHL:2) ;- (EBI) Number of wait states
AT91C_EBI_NWS_1 EQU (0x0:SHL:2) ;- (EBI) 1 wait state
AT91C_EBI_NWS_2 EQU (0x1:SHL:2) ;- (EBI) 2 wait state
AT91C_EBI_NWS_3 EQU (0x2:SHL:2) ;- (EBI) 3 wait state
AT91C_EBI_NWS_4 EQU (0x3:SHL:2) ;- (EBI) 4 wait state
AT91C_EBI_NWS_5 EQU (0x4:SHL:2) ;- (EBI) 5 wait state
AT91C_EBI_NWS_6 EQU (0x5:SHL:2) ;- (EBI) 6 wait state
AT91C_EBI_NWS_7 EQU (0x6:SHL:2) ;- (EBI) 7 wait state
AT91C_EBI_NWS_8 EQU (0x7:SHL:2) ;- (EBI) 8 wait state
AT91C_EBI_WSE EQU (0x1:SHL:5) ;- (EBI) Wait State Enable
AT91C_EBI_PAGES EQU (0x3:SHL:7) ;- (EBI) Pages Size
AT91C_EBI_PAGES_1M EQU (0x0:SHL:7) ;- (EBI) 1M Byte
AT91C_EBI_PAGES_4M EQU (0x1:SHL:7) ;- (EBI) 4M Byte
AT91C_EBI_PAGES_16M EQU (0x2:SHL:7) ;- (EBI) 16M Byte
AT91C_EBI_PAGES_64M EQU (0x3:SHL:7) ;- (EBI) 64M Byte
AT91C_EBI_TDF EQU (0x7:SHL:9) ;- (EBI) Data Float Output Time
AT91C_EBI_TDF_0 EQU (0x0:SHL:9) ;- (EBI) 1 TDF
AT91C_EBI_TDF_1 EQU (0x1:SHL:9) ;- (EBI) 2 TDF
AT91C_EBI_TDF_2 EQU (0x2:SHL:9) ;- (EBI) 3 TDF
AT91C_EBI_TDF_3 EQU (0x3:SHL:9) ;- (EBI) 4 TDF
AT91C_EBI_TDF_4 EQU (0x4:SHL:9) ;- (EBI) 5 TDF
AT91C_EBI_TDF_5 EQU (0x5:SHL:9) ;- (EBI) 6 TDF
AT91C_EBI_TDF_6 EQU (0x6:SHL:9) ;- (EBI) 7 TDF
AT91C_EBI_TDF_7 EQU (0x7:SHL:9) ;- (EBI) 8 TDF
AT91C_EBI_BAT EQU (0x1:SHL:12) ;- (EBI) Byte Access Type
AT91C_EBI_CSEN EQU (0x1:SHL:13) ;- (EBI) Chip Select Enable
AT91C_EBI_BA EQU (0xFFF:SHL:20) ;- (EBI) Base Address
;- -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register --------
AT91C_EBI_RCB EQU (0x1:SHL:0) ;- (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices.
;- -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register --------
AT91C_EBI_ALE EQU (0x7:SHL:0) ;- (EBI) Address Line Enable
AT91C_EBI_ALE_16M EQU (0x0) ;- (EBI) Valid Address Bits = A20, A21, A22, A23 Max Addressable Space = 16M Bytes Valid Chip Select=None
AT91C_EBI_ALE_8M EQU (0x4) ;- (EBI) Valid Address Bits = A20, A21, A22 Max Addressable Space = 8M Bytes Valid Chip Select = CS4
AT91C_EBI_ALE_4M EQU (0x5) ;- (EBI) Valid Address Bits = A20, A21 Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5
AT91C_EBI_ALE_2M EQU (0x6) ;- (EBI) Valid Address Bits = A20 Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6
AT91C_EBI_ALE_1M EQU (0x7) ;- (EBI) Valid Address Bits = None Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7
AT91C_EBI_DRP EQU (0x1:SHL:4) ;- (EBI)
;- *****************************************************************************
;- REGISTER ADDRESS DEFINITION FOR AT91M55800A
;- *****************************************************************************
;- ========== Register definition for AIC peripheral ==========
AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector egister
AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode egister
AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command egister
;- ========== Register definition for WD peripheral ==========
AT91C_WD_SR EQU (0xFFFF800C) ;- (WD) Status Register
AT91C_WD_CMR EQU (0xFFFF8004) ;- (WD) Clock Mode Register
AT91C_WD_CR EQU (0xFFFF8008) ;- (WD) Control Register
AT91C_WD_OMR EQU (0xFFFF8000) ;- (WD) Overflow Mode Register
;- ========== Register definition for APMC peripheral ==========
AT91C_APMC_SR EQU (0xFFFF4030) ;- (APMC) Status Register
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