at91m55800a.inc

前段时间做了一个AT91M55800的芯片测试

RTC_IMR         #  4 ;- Interrupt Mask Register
RTC_VER         #  4 ;- Valid Entry Register
;- -------- RTC_MR : (RTC Offset: 0x0) RTC Mode Register -------- 
AT91C_RTC_UPDTIM          EQU (0x1:SHL:0) ;- (RTC) Update Request Time Register
AT91C_RTC_UPDCAL          EQU (0x1:SHL:1) ;- (RTC) Update Request Calendar Register
AT91C_RTC_TEVSEL          EQU (0x3:SHL:8) ;- (RTC) Time Event Selection
AT91C_RTC_TEVSEL_MN_CHG   EQU (0x0:SHL:8) ;- (RTC) Minute change.
AT91C_RTC_TEVSEL_HR_CHG   EQU (0x1:SHL:8) ;- (RTC) Hour change.
AT91C_RTC_TEVSEL_EVDAY_MD EQU (0x2:SHL:8) ;- (RTC) Every day at midnight.
AT91C_RTC_TEVSEL_EVDAY_NOON EQU (0x3:SHL:8) ;- (RTC) Every day at noon.
AT91C_RTC_CEVSEL          EQU (0x3:SHL:16) ;- (RTC) Calendar Event Selection
AT91C_RTC_CEVSEL_WEEK_CHG EQU (0x0:SHL:16) ;- (RTC) Week change (every Monday at time 00:00:00).
AT91C_RTC_CEVSEL_MONTH_CHG EQU (0x1:SHL:16) ;- (RTC) Month change (every 01 of each month at time 00:00:00).
AT91C_RTC_CEVSEL_YEAR_CHG EQU (0x2:SHL:16) ;- (RTC) Year change (every January 1 at time 00:00:00).
;- -------- RTC_HMR : (RTC Offset: 0x4) RTC Hour Mode Register -------- 
AT91C_RTC_HRMOD           EQU (0x1:SHL:0) ;- (RTC) 12-24 hour Mode
;- -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- 
AT91C_RTC_SEC             EQU (0x7F:SHL:0) ;- (RTC) Current Second
AT91C_RTC_MIN             EQU (0x7F:SHL:8) ;- (RTC) Current Minute
AT91C_RTC_HOUR            EQU (0x3F:SHL:16) ;- (RTC) Current Hour
AT91C_RTC_AMPM            EQU (0x1:SHL:22) ;- (RTC) Ante Meridiem, Post Meridiem Indicator
;- -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- 
AT91C_RTC_CENT            EQU (0x3F:SHL:0) ;- (RTC) Current Century
AT91C_RTC_YEAR            EQU (0xFF:SHL:8) ;- (RTC) Current Year
AT91C_RTC_MONTH           EQU (0x1F:SHL:16) ;- (RTC) Current Month
AT91C_RTC_DAY             EQU (0x7:SHL:21) ;- (RTC) Current Day
AT91C_RTC_DATE            EQU (0x3F:SHL:24) ;- (RTC) Current Date
;- -------- RTC_TAR : (RTC Offset: 0x10) RTC Time Alarm Register -------- 
AT91C_RTC_SECEN           EQU (0x1:SHL:7) ;- (RTC) Second Alarm Enable
AT91C_RTC_MINEN           EQU (0x1:SHL:15) ;- (RTC) Minute Alarm
AT91C_RTC_HOUREN          EQU (0x1:SHL:23) ;- (RTC) Current Hour
;- -------- RTC_CAR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- 
AT91C_RTC_MTHEN           EQU (0x1:SHL:23) ;- (RTC) Month Alarm Enable
AT91C_RTC_DATEN           EQU (0x1:SHL:31) ;- (RTC) Date Alarm Enable
;- -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- 
AT91C_RTC_ACKUPD          EQU (0x1:SHL:0) ;- (RTC) Acknowledge for Update
AT91C_RTC_ALARM           EQU (0x1:SHL:1) ;- (RTC) Alarm Flag
AT91C_RTC_SECEV           EQU (0x1:SHL:2) ;- (RTC) Second Event
AT91C_RTC_TIMEV           EQU (0x1:SHL:3) ;- (RTC) Time Event
AT91C_RTC_CALEV           EQU (0x1:SHL:4) ;- (RTC) Calendar event
;- -------- RTC_SCR : (RTC Offset: 0x1c) RTC Status Clear Register -------- 
;- -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- 
;- -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- 
;- -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- 
;- -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- 
AT91C_RTC_NVT             EQU (0x1:SHL:0) ;- (RTC) Non valid Time
AT91C_RTC_NVC             EQU (0x1:SHL:1) ;- (RTC) Non valid Calendar
AT91C_RTC_NVTAL           EQU (0x1:SHL:2) ;- (RTC) Non valid time Alarm
AT91C_RTC_NVCAL           EQU (0x1:SHL:3) ;- (RTC) Nonvalid Calendar Alarm

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
;- *****************************************************************************
                ^ 0 ;- AT91S_PIO
PIO_PER         #  4 ;- PIO Enable Register
PIO_PDR         #  4 ;- PIO Disable Register
PIO_PSR         #  4 ;- PIO Status Register
                #  4 ;- Reserved
PIO_OER         #  4 ;- Output Enable Register
PIO_ODR         #  4 ;- Output Disable Registerr
PIO_OSR         #  4 ;- Output Status Register
                #  4 ;- Reserved
PIO_IFER        #  4 ;- Input Filter Enable Register
PIO_IFDR        #  4 ;- Input Filter Disable Register
PIO_IFSR        #  4 ;- Input Filter Status Register
                #  4 ;- Reserved
PIO_SODR        #  4 ;- Set Output Data Register
PIO_CODR        #  4 ;- Clear Output Data Register
PIO_ODSR        #  4 ;- Output Data Status Register
PIO_PDSR        #  4 ;- Pin Data Status Register
PIO_IER         #  4 ;- Interrupt Enable Register
PIO_IDR         #  4 ;- Interrupt Disable Register
PIO_IMR         #  4 ;- Interrupt Mask Register
PIO_ISR         #  4 ;- Interrupt Status Register
PIO_MDER        #  4 ;- Multi-driver Enable Register
PIO_MDDR        #  4 ;- Multi-driver Disable Register
PIO_MDSR        #  4 ;- Multi-driver Status Register

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
;- *****************************************************************************
                ^ 0 ;- AT91S_TC
TC_CCR          #  4 ;- Channel Control Register
TC_CMR          #  4 ;- Channel Mode Register
                #  8 ;- Reserved
TC_CV           #  4 ;- Counter Value
TC_RA           #  4 ;- Register A
TC_RB           #  4 ;- Register B
TC_RC           #  4 ;- Register C
TC_SR           #  4 ;- Status Register
TC_IER          #  4 ;- Interrupt Enable Register
TC_IDR          #  4 ;- Interrupt Disable Register
TC_IMR          #  4 ;- Interrupt Mask Register
;- -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
AT91C_TC_CLKEN            EQU (0x1:SHL:0) ;- (TC) Counter Clock Enable Command
AT91C_TC_CLKDIS           EQU (0x1:SHL:1) ;- (TC) Counter Clock Disable Command
AT91C_TC_SWTRG            EQU (0x1:SHL:2) ;- (TC) Software Trigger Command
;- -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
AT91C_TC_CPCSTOP          EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RC Compare
AT91C_TC_CPCDIS           EQU (0x1:SHL:7) ;- (TC) Counter Clock Disable with RC Compare
AT91C_TC_EEVTEDG          EQU (0x3:SHL:8) ;- (TC) External Event Edge Selection
AT91C_TC_EEVTEDG_NONE     EQU (0x0:SHL:8) ;- (TC) Edge: None
AT91C_TC_EEVTEDG_RISING   EQU (0x1:SHL:8) ;- (TC) Edge: rising edge
AT91C_TC_EEVTEDG_FALLING  EQU (0x2:SHL:8) ;- (TC) Edge: falling edge
AT91C_TC_EEVTEDG_BOTH     EQU (0x3:SHL:8) ;- (TC) Edge: each edge
AT91C_TC_EEVT             EQU (0x3:SHL:10) ;- (TC) External Event  Selection
AT91C_TC_EEVT_NONE        EQU (0x0:SHL:10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
AT91C_TC_EEVT_RISING      EQU (0x1:SHL:10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
AT91C_TC_EEVT_FALLING     EQU (0x2:SHL:10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
AT91C_TC_EEVT_BOTH        EQU (0x3:SHL:10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
AT91C_TC_ENETRG           EQU (0x1:SHL:12) ;- (TC) External Event Trigger enable
AT91C_TC_WAVESEL          EQU (0x3:SHL:13) ;- (TC) Waveform  Selection
AT91C_TC_WAVESEL_UP       EQU (0x0:SHL:13) ;- (TC) UP mode without atomatic trigger on RC Compare
AT91C_TC_WAVESEL_UP_AUTO  EQU (0x1:SHL:13) ;- (TC) UP mode with automatic trigger on RC Compare
AT91C_TC_WAVESEL_UPDOWN   EQU (0x2:SHL:13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3:SHL:13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
AT91C_TC_CPCTRG           EQU (0x1:SHL:14) ;- (TC) RC Compare Trigger Enable
AT91C_TC_WAVE             EQU (0x1:SHL:15) ;- (TC) 
AT91C_TC_ACPA             EQU (0x3:SHL:16) ;- (TC) RA Compare Effect on TIOA
AT91C_TC_ACPA_NONE        EQU (0x0:SHL:16) ;- (TC) Effect: none
AT91C_TC_ACPA_SET         EQU (0x1:SHL:16) ;- (TC) Effect: set
AT91C_TC_ACPA_CLEAR       EQU (0x2:SHL:16) ;- (TC) Effect: clear
AT91C_TC_ACPA_TOGGLE      EQU (0x3:SHL:16) ;- (TC) Effect: toggle
AT91C_TC_ACPC             EQU (0x3:SHL:18) ;- (TC) RC Compare Effect on TIOA
AT91C_TC_ACPC_NONE        EQU (0x0:SHL:18) ;- (TC) Effect: none
AT91C_TC_ACPC_SET         EQU (0x1:SHL:18) ;- (TC) Effect: set
AT91C_TC_ACPC_CLEAR       EQU (0x2:SHL:18) ;- (TC) Effect: clear
AT91C_TC_ACPC_TOGGLE      EQU (0x3:SHL:18) ;- (TC) Effect: toggle
AT91C_TC_AEEVT            EQU (0x3:SHL:20) ;- (TC) External Event Effect on TIOA
AT91C_TC_AEEVT_NONE       EQU (0x0:SHL:20) ;- (TC) Effect: none
AT91C_TC_AEEVT_SET        EQU (0x1:SHL:20) ;- (TC) Effect: set
AT91C_TC_AEEVT_CLEAR      EQU (0x2:SHL:20) ;- (TC) Effect: clear
AT91C_TC_AEEVT_TOGGLE     EQU (0x3:SHL:20) ;- (TC) Effect: toggle
AT91C_TC_ASWTRG           EQU (0x3:SHL:22) ;- (TC) Software Trigger Effect on TIOA
AT91C_TC_ASWTRG_NONE      EQU (0x0:SHL:22) ;- (TC) Effect: none
AT91C_TC_ASWTRG_SET       EQU (0x1:SHL:22) ;- (TC) Effect: set
AT91C_TC_ASWTRG_CLEAR     EQU (0x2:SHL:22) ;- (TC) Effect: clear
AT91C_TC_ASWTRG_TOGGLE    EQU (0x3:SHL:22) ;- (TC) Effect: toggle
AT91C_TC_BCPB             EQU (0x3:SHL:24) ;- (TC) RB Compare Effect on TIOB
AT91C_TC_BCPB_NONE        EQU (0x0:SHL:24) ;- (TC) Effect: none
AT91C_TC_BCPB_SET         EQU (0x1:SHL:24) ;- (TC) Effect: set
AT91C_TC_BCPB_CLEAR       EQU (0x2:SHL:24) ;- (TC) Effect: clear
AT91C_TC_BCPB_TOGGLE      EQU (0x3:SHL:24) ;- (TC) Effect: toggle
AT91C_TC_BCPC             EQU (0x3:SHL:26) ;- (TC) RC Compare Effect on TIOB
AT91C_TC_BCPC_NONE        EQU (0x0:SHL:26) ;- (TC) Effect: none
AT91C_TC_BCPC_SET         EQU (0x1:SHL:26) ;- (TC) Effect: set
AT91C_TC_BCPC_CLEAR       EQU (0x2:SHL:26) ;- (TC) Effect: clear
AT91C_TC_BCPC_TOGGLE      EQU (0x3:SHL:26) ;- (TC) Effect: toggle
AT91C_TC_BEEVT            EQU (0x3:SHL:28) ;- (TC) External Event Effect on TIOB
AT91C_TC_BEEVT_NONE       EQU (0x0:SHL:28) ;- (TC) Effect: none
AT91C_TC_BEEVT_SET        EQU (0x1:SHL:28) ;- (TC) Effect: set
AT91C_TC_BEEVT_CLEAR      EQU (0x2:SHL:28) ;- (TC) Effect: clear
AT91C_TC_BEEVT_TOGGLE     EQU (0x3:SHL:28) ;- (TC) Effect: toggle
AT91C_TC_BSWTRG           EQU (0x3:SHL:30) ;- (TC) Software Trigger Effect on TIOB
AT91C_TC_BSWTRG_NONE      EQU (0x0:SHL:30) ;- (TC) Effect: none
AT91C_TC_BSWTRG_SET       EQU (0x1:SHL:30) ;- (TC) Effect: set
AT91C_TC_BSWTRG_CLEAR     EQU (0x2:SHL:30) ;- (TC) Effect: clear
AT91C_TC_BSWTRG_TOGGLE    EQU (0x3:SHL:30) ;- (TC) Effect: toggle
;- -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
AT91C_TC_COVFS            EQU (0x1:SHL:0) ;- (TC) Counter Overflow
AT91C_TC_LOVRS            EQU (0x1:SHL:1) ;- (TC) Load Overrun
AT91C_TC_CPAS             EQU (0x1:SHL:2) ;- (TC) RA Compare
AT91C_TC_CPBS             EQU (0x1:SHL:3) ;- (TC) RB Compare
AT91C_TC_CPCS             EQU (0x1:SHL:4) ;- (TC) RC Compare
AT91C_TC_LDRAS            EQU (0x1:SHL:5) ;- (TC) RA Loading
AT91C_TC_LDRBS            EQU (0x1:SHL:6) ;- (TC) RB Loading
AT91C_TC_ETRCS            EQU (0x1:SHL:7) ;- (TC) External Trigger
AT91C_TC_ETRGS            EQU (0x1:SHL:16) ;- (TC) Clock Enabling
AT91C_TC_MTIOA            EQU (0x1:SHL:17) ;- (TC) TIOA Mirror
AT91C_TC_MTIOB            EQU (0x1:SHL:18) ;- (TC) TIOA Mirror
;- -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
;- -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
;- -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Timer Counter Interface
;- *****************************************************************************
                ^ 0 ;- AT91S_TCB
TCB_TC0         # 48 ;- TC Channel 0
                # 16 ;- Reserved
TCB_TC1         # 48 ;- TC Channel 1
                # 16 ;- Reserved
TCB_TC2         # 48 ;- TC Channel 2
                # 16 ;- Reserved
TCB_BCR         #  4 ;- TC Block Control Register
TCB_BMR         #  4 ;- TC Block Mode Register
;- -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
AT91C_TCB_SYNC            EQU (0x1:SHL:0) ;- (TCB) Synchro Command
;- -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
AT91C_TCB_TC0XC0S         EQU (0x1:SHL:0) ;- (TCB) External Clock Signal 0 Selection
AT91C_TCB_TC0XC0S_TCLK0   EQU (0x0) ;- (TCB) TCLK0 connected to XC0