at91m55800a.inc

前段时间做了一个AT91M55800的芯片测试

;- ----------------------------------------------------------------------------
;-          ATMEL Microcontroller Software Support  -  ROUSSET  -
;- ----------------------------------------------------------------------------
;-  The software is delivered "AS IS" without warranty or condition of any
;-  kind, either express, implied or statutory. This includes without
;-  limitation any warranty or condition with respect to merchantability or
;-  fitness for any particular purpose, or against the infringements of
;-  intellectual property rights of others.
;- ----------------------------------------------------------------------------
;- File Name           : AT91M55800A.h
;- Object              : AT91M55800A definitions
;- Generated           : AT91 SW Application Group  07/01/2003 (17:21:53)
;- 
;- CVS Reference       : /AT91M55800A.pl/1.18/Thu Nov 21 12:37:56 2002//
;- CVS Reference       : /AIC_1246F.pl/1.4/Mon Nov 04 16:50:58 2002//
;- CVS Reference       : /WD_1241B.pl/1.1/Mon Nov 04 16:51:00 2002//
;- CVS Reference       : /APMC_55800A.pl/1.1/Thu Nov 21 12:37:30 2002//
;- CVS Reference       : /RTC_1366C.pl/1.2/Mon Nov 04 16:50:58 2002//
;- CVS Reference       : /PIO_1321C.pl/1.5/Tue Oct 29 14:50:24 2002//
;- CVS Reference       : /TC_1243B.pl/1.4/Tue Nov 05 11:43:10 2002//
;- CVS Reference       : /PDC_1363D.pl/1.3/Wed Oct 23 13:49:46 2002//
;- CVS Reference       : /US_1242E.pl/1.5/Thu Nov 21 12:37:56 2002//
;- CVS Reference       : /SPI_1244C.pl/1.5/Tue Nov 05 16:13:46 2002//
;- CVS Reference       : /ADC_55800A.pl/1.3/Tue Nov 05 16:02:02 2002//
;- CVS Reference       : /DAC_55800A.pl/1.1/Tue Nov 05 11:43:10 2002//
;- CVS Reference       : /SF_M55800A.pl/1.1/Tue Nov 05 14:45:40 2002//
;- CVS Reference       : /EBI_55800A.pl/1.3/Wed Feb 19 08:25:20 2003//
;- ----------------------------------------------------------------------------

;- Hardware register definition

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
;- *****************************************************************************
                ^ 0 ;- AT91S_AIC
AIC_SMR         # 128 ;- Source Mode egister
AIC_SVR         # 128 ;- Source Vector egister
AIC_IVR         #  4 ;- IRQ Vector Register
AIC_FVR         #  4 ;- FIQ Vector Register
AIC_ISR         #  4 ;- Interrupt Status Register
AIC_IPR         #  4 ;- Interrupt Pending Register
AIC_IMR         #  4 ;- Interrupt Mask Register
AIC_CISR        #  4 ;- Core Interrupt Status Register
                #  8 ;- Reserved
AIC_IECR        #  4 ;- Interrupt Enable Command Register
AIC_IDCR        #  4 ;- Interrupt Disable Command egister
AIC_ICCR        #  4 ;- Interrupt Clear Command Register
AIC_ISCR        #  4 ;- Interrupt Set Command Register
AIC_EOICR       #  4 ;- End of Interrupt Command Register
AIC_SPU         #  4 ;- Spurious Vector Register
;- -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
AT91C_AIC_PRIOR           EQU (0x7:SHL:0) ;- (AIC) Priority Level
AT91C_AIC_PRIOR_LOWEST    EQU (0x0) ;- (AIC) Lowest priority level
AT91C_AIC_PRIOR_HIGHEST   EQU (0x7) ;- (AIC) Highest priority level
AT91C_AIC_SRCTYPE         EQU (0x3:SHL:5) ;- (AIC) Interrupt Source Type
AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE EQU (0x0:SHL:5) ;- (AIC) Internal Sources Code Label Level Sensitive
AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED EQU (0x1:SHL:5) ;- (AIC) Internal Sources Code Label Edge triggered
AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL EQU (0x2:SHL:5) ;- (AIC) External Sources Code Label High-level Sensitive
AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE EQU (0x3:SHL:5) ;- (AIC) External Sources Code Label Positive Edge triggered
;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
AT91C_AIC_NFIQ            EQU (0x1:SHL:0) ;- (AIC) NFIQ Status
AT91C_AIC_NIRQ            EQU (0x1:SHL:1) ;- (AIC) NIRQ Status

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Watchdog Timer Interface
;- *****************************************************************************
                ^ 0 ;- AT91S_WD
WD_OMR          #  4 ;- Overflow Mode Register
WD_CMR          #  4 ;- Clock Mode Register
WD_CR           #  4 ;- Control Register
WD_SR           #  4 ;- Status Register
;- -------- WD_OMR : (WD Offset: 0x0) Overflow Mode Register -------- 
AT91C_WD_WDEN             EQU (0x1:SHL:0) ;- (WD) Watchdog Enable
AT91C_WD_RSTEN            EQU (0x1:SHL:1) ;- (WD) Reset Enable
AT91C_WD_IRQEN            EQU (0x1:SHL:2) ;- (WD) Interrupt Enable
AT91C_WD_EXTEN            EQU (0x1:SHL:3) ;- (WD) External Signal Enable
AT91C_WD_OKEY             EQU (0xFFF:SHL:4) ;- (WD) Watchdog Enable
;- -------- WD_CMR : (WD Offset: 0x4) Clock Mode Register -------- 
AT91C_WD_WDCLKS           EQU (0x3:SHL:0) ;- (WD) Clock Selection
AT91C_WD_WDCLKS_MCK32     EQU (0x0) ;- (WD) Master Clock divided by 32
AT91C_WD_WDCLKS_MCK128    EQU (0x1) ;- (WD) Master Clock divided by 128
AT91C_WD_WDCLKS_MCK1024   EQU (0x2) ;- (WD) Master Clock divided by 1024
AT91C_WD_WDCLKS_MCK4096   EQU (0x3) ;- (WD) Master Clock divided by 4096
AT91C_WD_HPCV             EQU (0xF:SHL:2) ;- (WD) High Pre-load Counter Value
AT91C_WD_CKEY             EQU (0x1FF:SHL:7) ;- (WD) Clock Access Key
;- -------- WD_CR : (WD Offset: 0x8) Control Register -------- 
AT91C_WD_RSTKEY           EQU (0xFFFF:SHL:0) ;- (WD) Restart Key
;- -------- WD_SR : (WD Offset: 0xc) Status Register -------- 
AT91C_WD_WDOVF            EQU (0x1:SHL:0) ;- (WD) Watchdog Overflow

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Advanced Power Management Controler
;- *****************************************************************************
                ^ 0 ;- AT91S_APMC
APMC_SCER       #  4 ;- System Clock Enable Register
APMC_SCDR       #  4 ;- System Clock Disable Register
APMC_SCSR       #  4 ;- System Clock Status Register
                #  4 ;- Reserved
APMC_PCER       #  4 ;- Peripheral Clock Enable Register
APMC_PCDR       #  4 ;- Peripheral Clock Disable Register
APMC_PCSR       #  4 ;- Peripheral Clock Status Register
                #  4 ;- Reserved
APMC_CGMR       #  4 ;- Clock Generator Mode Register
                #  4 ;- Reserved
APMC_PCR        #  4 ;- Power Control Register
APMC_PMR        #  4 ;- Power Mode Register
APMC_SR         #  4 ;- Status Register
APMC_IER        #  4 ;- Interrupt Enable Register
APMC_IDR        #  4 ;- Interrupt Disable Register
APMC_IMR        #  4 ;- Interrupt Mask Register
;- -------- APMC_SCER : (APMC Offset: 0x0) System Clock Enable Register -------- 
AT91C_APMC_CPU            EQU (0x1:SHL:0) ;- (APMC) System Clock
;- -------- APMC_SCDR : (APMC Offset: 0x4) System Clock Disable Register -------- 
;- -------- APMC_SCSR : (APMC Offset: 0x8) System Clock Status Register -------- 
;- -------- APMC_PCER : (APMC Offset: 0x10) Peripheral Clock Enable Register -------- 
AT91C_APMC_US0            EQU (0x1:SHL:2) ;- (APMC) Usart 0 Clock
AT91C_APMC_US1            EQU (0x1:SHL:3) ;- (APMC) Usart 1 Clock
AT91C_APMC_US2            EQU (0x1:SHL:4) ;- (APMC) Usart 2 Clock
AT91C_APMC_SPI            EQU (0x1:SHL:5) ;- (APMC) Serial Peripheral Interface Clock
AT91C_APMC_TC0            EQU (0x1:SHL:6) ;- (APMC) Timer Counter 0 Clock
AT91C_APMC_TC1            EQU (0x1:SHL:7) ;- (APMC) Timer Counter 1 Clock
AT91C_APMC_TC2            EQU (0x1:SHL:8) ;- (APMC) Timer Counter 2 Clock
AT91C_APMC_TC3            EQU (0x1:SHL:9) ;- (APMC) Timer Counter 3 Clock
AT91C_APMC_TC4            EQU (0x1:SHL:10) ;- (APMC) Timer Counter 4 Clock
AT91C_APMC_TC5            EQU (0x1:SHL:11) ;- (APMC) Timer Counter 5 Clock
AT91C_APMC_PIOA           EQU (0x1:SHL:13) ;- (APMC) PIOA  Clock
AT91C_APMC_PIOB           EQU (0x1:SHL:14) ;- (APMC) PIOB Clock
AT91C_APMC_ADC0           EQU (0x1:SHL:15) ;- (APMC) Analog to Digital Converter 0 Clock
AT91C_APMC_ADC1           EQU (0x1:SHL:16) ;- (APMC) Analog to Digital Converter 1 Clock
AT91C_APMC_DAC0           EQU (0x1:SHL:17) ;- (APMC) Digital to Analog Converter 0 Clock
AT91C_APMC_DAC1           EQU (0x1:SHL:18) ;- (APMC) Digital to Analog Converter 1 Clock
;- -------- APMC_PCDR : (APMC Offset: 0x14) Peripheral Clock Disable Register -------- 
;- -------- APMC_PCSR : (APMC Offset: 0x18) Peripheral Clock Satus Register -------- 
;- -------- APMC_CGMR : (APMC Offset: 0x20) Clock Generator Mode Register -------- 
AT91C_APMC_MOSCBYP        EQU (0x1:SHL:0) ;- (APMC) Main Oscillator Bypass
AT91C_APMC_MOSCEN         EQU (0x1:SHL:1) ;- (APMC) Main Oscillator Enable
AT91C_APMC_MCKODS         EQU (0x1:SHL:2) ;- (APMC) Master Clock Output Disable
AT91C_APMC_PRES           EQU (0x7:SHL:4) ;- (APMC) Prescaler Selection
AT91C_APMC_PRES_NONE      EQU (0x0:SHL:4) ;- (APMC) Prescaler Output is the selected clock
AT91C_APMC_PRES_DIV2      EQU (0x1:SHL:4) ;- (APMC) Selected clock is divided by 2
AT91C_APMC_PRES_DIV4      EQU (0x2:SHL:4) ;- (APMC) Selected clock is divided by 4
AT91C_APMC_PRES_DIV8      EQU (0x3:SHL:4) ;- (APMC) Selected clock is divided by 8
AT91C_APMC_PRES_DIV16     EQU (0x4:SHL:4) ;- (APMC) Selected clock is divided by 16
AT91C_APMC_PRES_DIV32     EQU (0x5:SHL:4) ;- (APMC) Selected clock is divided by 32
AT91C_APMC_PRES_DIV64     EQU (0x6:SHL:4) ;- (APMC) Selected clock is divided by 64
AT91C_APMC_MUL            EQU (0x3F:SHL:8) ;- (APMC) Phase Lock Loop Factor
AT91C_APMC_CSS            EQU (0x3:SHL:14) ;- (APMC) Clock Source Selection
AT91C_APMC_CSS_LF         EQU (0x0:SHL:14) ;- (APMC) Low-frequency clock provided by the RTC
AT91C_APMC_CSS_MOSC       EQU (0x1:SHL:14) ;- (APMC) Main Oscillator Output or external clock
AT91C_APMC_CSS_PLL        EQU (0x2:SHL:14) ;- (APMC) Phase Locked Loop Output
AT91C_APMC_OSCOUNT        EQU (0x3F:SHL:16) ;- (APMC) Main Oscillator Counter
AT91C_APMC_PLLCOUNT       EQU (0x1:SHL:24) ;- (APMC) PLL Lock Counter
;- -------- APMC_PCR : (APMC Offset: 0x28) Power Control Register -------- 
AT91C_APMC_SHDALC         EQU (0x1:SHL:0) ;- (APMC) Shut-down or Alarm Command
AT91C_APMC_WKACKC         EQU (0x1:SHL:1) ;- (APMC) Wake-up or Alarm Acknoledge Command
;- -------- APMC_PMR : (APMC Offset: 0x2c) Power Mode Register -------- 
AT91C_APMC_SHDALS         EQU (0x3:SHL:0) ;- (APMC) Shut-down or Alarm Command
AT91C_APMC_SHDALS_OUT_TRIS EQU (0x0) ;- (APMC) Tri-stated
AT91C_APMC_SHDALS_OUT_LEVEL0 EQU (0x1) ;- (APMC) Level 0
AT91C_APMC_SHDALS_OUT_LEVEL1 EQU (0x2) ;- (APMC) Level 1
AT91C_APMC_WKACKS         EQU (0x1:SHL:2) ;- (APMC) Wake-up or Alarm Acknoledge Command
AT91C_APMC_WKACKS_OUT_TRIS EQU (0x0:SHL:2) ;- (APMC) Tri-stated
AT91C_APMC_WKACKS_OUT_LEVEL0 EQU (0x1:SHL:2) ;- (APMC) Level 0
AT91C_APMC_WKACKS_OUT_LEVEL1 EQU (0x2:SHL:2) ;- (APMC) Level 1
AT91C_APMC_ALWKEN         EQU (0x1:SHL:4) ;- (APMC) Alarm Wake-up Enable
AT91C_APMC_WKEDG          EQU (0x3:SHL:6) ;- (APMC) Wake-up Input Edge Selection
AT91C_APMC_WKEDG_NONE     EQU (0x0:SHL:6) ;- (APMC) None. No edge is detected on wake-up
AT91C_APMC_WKEDG_POS_EDG  EQU (0x1:SHL:6) ;- (APMC) Positive edge
AT91C_APMC_WKEDG_NEG_EDG  EQU (0x2:SHL:6) ;- (APMC) Negative edge
AT91C_APMC_WKEDG_BOTH_EDG EQU (0x3:SHL:6) ;- (APMC) Both edges 
;- -------- APMC_SR : (APMC Offset: 0x30) APMC Status Register -------- 
AT91C_APMC_MOSCS          EQU (0x1:SHL:0) ;- (APMC) Main Oscillator Status
AT91C_APMC_LOCK           EQU (0x1:SHL:1) ;- (APMC) PLL Lock Status
;- -------- APMC_IER : (APMC Offset: 0x34) APMC Interrupt Enable Register -------- 
;- -------- APMC_IDR : (APMC Offset: 0x38) APMC Interrupt Disable Register -------- 
;- -------- APMC_IMR : (APMC Offset: 0x3c) APMC Interrupt Mask Register -------- 

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR Real-time Clock Alarm
;- *****************************************************************************
                ^ 0 ;- AT91S_RTC
RTC_MR          #  4 ;- Mode Register
RTC_HMR         #  4 ;- Hour Mode Register
RTC_TIMR        #  4 ;- Time Register
RTC_CALR        #  4 ;- Calendar Register
RTC_TAR         #  4 ;- Time Alarm Register
RTC_CAR         #  4 ;- Calendar Alarm Register
RTC_SR          #  4 ;- Status Register
RTC_SCR         #  4 ;- Status Clear Register
RTC_IER         #  4 ;- Interrupt Enable Register
RTC_IDR         #  4 ;- Interrupt Disable Register