cy7c67200_300.h

USB Host 资料

#define DEV1_EP4_CNT_REG                                     0x0244 /* Device 1 Endpoint 4 Count Register [R/W] */
#define DEV1_EP5_CNT_REG                                     0x0254 /* Device 1 Endpoint 5 Count Register [R/W] */
#define DEV1_EP6_CNT_REG                                     0x0264 /* Device 1 Endpoint 6 Count Register [R/W] */
#define DEV1_EP7_CNT_REG                                     0x0274 /* Device 1 Endpoint 7 Count Register [R/W] */

#define DEV2_EP0_CNT_REG                                     0x0284 /* Device 2 Endpoint 0 Count Register [R/W] */
#define DEV2_EP1_CNT_REG                                     0x0294 /* Device 2 Endpoint 1 Count Register [R/W]      */
#define DEV2_EP2_CNT_REG                                     0x02A4 /* Device 2 Endpoint 2 Count Register [R/W] */
#define DEV2_EP3_CNT_REG                                     0x02B4 /* Device 2 Endpoint 3 Count Register [R/W] */
#define DEV2_EP4_CNT_REG                                     0x02C4 /* Device 2 Endpoint 4 Count Register [R/W] */
#define DEV2_EP5_CNT_REG                                     0x02D4 /* Device 2 Endpoint 5 Count Register [R/W] */
#define DEV2_EP6_CNT_REG                                     0x02E4 /* Device 2 Endpoint 6 Count Register [R/W] */
#define DEV2_EP7_CNT_REG                                     0x02F4 /* Device 2 Endpoint 7 Count Register [R/W] */

/* FIELDS */

#define EP_CNT                                               0x03FF /* Endpoint Count */

/*********************************************************/
/* DEVICE n ENDPOINT n STATUS REGISTERS [R/W]            */
/*********************************************************/

#define DEV1_EP0_STAT_REG                                    0x0206 /* Device 1 Endpoint 0 Status Register [R/W] */
#define DEV1_EP1_STAT_REG                                    0x0216 /* Device 1 Endpoint 1 Status Register [R/W]       */
#define DEV1_EP2_STAT_REG                                    0x0226 /* Device 1 Endpoint 2 Status Register [R/W] */
#define DEV1_EP3_STAT_REG                                    0x0236 /* Device 1 Endpoint 3 Status Register [R/W] */
#define DEV1_EP4_STAT_REG                                    0x0246 /* Device 1 Endpoint 4 Status Register [R/W] */
#define DEV1_EP5_STAT_REG                                    0x0256 /* Device 1 Endpoint 5 Status Register [R/W] */
#define DEV1_EP6_STAT_REG                                    0x0266 /* Device 1 Endpoint 6 Status Register [R/W] */
#define DEV1_EP7_STAT_REG                                    0x0276 /* Device 1 Endpoint 7 Status Register [R/W] */

#define DEV2_EP0_STAT_REG                                    0x0286 /* Device 2 Endpoint 0 Status Register [R/W] */
#define DEV2_EP1_STAT_REG                                    0x0296 /* Device 2 Endpoint 1 Status Register [R/W]      */
#define DEV2_EP2_STAT_REG                                    0x02A6 /* Device 2 Endpoint 2 Status Register [R/W] */
#define DEV2_EP3_STAT_REG                                    0x02B6 /* Device 2 Endpoint 3 Status Register [R/W] */
#define DEV2_EP4_STAT_REG                                    0x02C6 /* Device 2 Endpoint 4 Status Register [R/W] */
#define DEV2_EP5_STAT_REG                                    0x02D6 /* Device 2 Endpoint 5 Status Register [R/W] */
#define DEV2_EP6_STAT_REG                                    0x02E6 /* Device 2 Endpoint 6 Status Register [R/W] */
#define DEV2_EP7_STAT_REG                                    0x02F6 /* Device 2 Endpoint 7 Status Register [R/W] */

/* FIELDS */

/* Defined in HOST n ENDPOINT STATUS REGISTERS
 * #define OVERFLOW_FLG                                      0x0800 /# Receive overflow #/
 * #define UNDERFLOW_FLG                                     0x0400 /# Receive underflow #/
 * #define STALL_FLG                                         0x0080 /# Stall sent #/
 * #define NAK_FLG                                           0x0040 /# NAK sent #/
 * #define LENGTH_EXCEPT_FLG                                 0x0020 /# Overflow or Underflow occured #/
 * #define SEQ_STAT                                          0x0008 /# Last Data Toggle Sequence bit sent or received #/
 * #define TIMEOUT_FLG                                       0x0004 /# Last transmission timed out #/
 * #define ERROR_FLG                                         0x0002 /# CRC Error detected in last reception #/
 * #define ACK_FLG                                           0x0001 /# Last transaction ACK'D (sent or received) #/
 */ 
#define OUT_EXCEPTION_FLG                                    0x0200 /* OUT received when armed for IN */
#define IN_EXCEPTION_FLG                                     0x0100 /* IN received when armed for OUT */
#define SETUP_FLG                                            0x0010 /* SETUP packet received */

/*********************************************************/
/* DEVICE n ENDPOINT n COUNT RESULT REGISTERS [R]      */
/*********************************************************/

#define DEV1_EP0_CTR_REG                                     0x0208 /* Device 1 Endpoint 0 Count Result Register [R] */
#define DEV1_EP1_CTR_REG                                     0x0218 /* Device 1 Endpoint 1 Count Result Register [R]       */
#define DEV1_EP2_CTR_REG                                     0x0228 /* Device 1 Endpoint 2 Count Result Register [R] */
#define DEV1_EP3_CTR_REG                                     0x0238 /* Device 1 Endpoint 3 Count Result Register [R] */
#define DEV1_EP4_CTR_REG                                     0x0248 /* Device 1 Endpoint 4 Count Result Register [R] */
#define DEV1_EP5_CTR_REG                                     0x0258 /* Device 1 Endpoint 5 Count Result Register [R] */
#define DEV1_EP6_CTR_REG                                     0x0268 /* Device 1 Endpoint 6 Count Result Register [R] */
#define DEV1_EP7_CTR_REG                                     0x0278 /* Device 1 Endpoint 7 Count Result Register [R] */

#define DEV2_EP0_CTR_REG                                     0x0288 /* Device 2 Endpoint 0 Count Result Register [R] */
#define DEV2_EP1_CTR_REG                                     0x0298 /* Device 2 Endpoint 1 Count Result Register [R]       */
#define DEV2_EP2_CTR_REG                                     0x02A8 /* Device 2 Endpoint 2 Count Result Register [R] */
#define DEV2_EP3_CTR_REG                                     0x02B8 /* Device 2 Endpoint 3 Count Result Register [R] */
#define DEV2_EP4_CTR_REG                                     0x02C8 /* Device 2 Endpoint 4 Count Result Register [R] */
#define DEV2_EP5_CTR_REG                                     0x02D8 /* Device 2 Endpoint 5 Count Result Register [R] */
#define DEV2_EP6_CTR_REG                                     0x02E8 /* Device 2 Endpoint 6 Count Result Register [R] */
#define DEV2_EP7_CTR_REG                                     0x02F8 /* Device 2 Endpoint 7 Count Result Register [R] */

/* FIELDS */

#define EP_RESULT                                            0x00FF /* Endpoint Count Result */


/*********************************************************/
/*********************************************************/
/* OTG REGISTERS                                         */
/*********************************************************/
/*********************************************************/

/*********************************************************/
/* OTG CONTROL REGISTER [R/W]                            */
/*********************************************************/

#define OTG_CTL_REG                                          0xC098 /* On-The-Go Control Register [R/W] */

/* FIELDS */

#define VBUS_PULLUP_EN                                       0x2000 /* Enable VBUS Pullup */
#define OTG_RX_DIS                                           0x1000 /* Disable OTG receiver */
#define CHG_PUMP_EN                                          0x0800 /* OTG Charge Pump enable */
#define VBUS_DISCH_EN                                        0x0400 /* VBUS discharge enable */
#define DPLUS_PULLUP_EN                                      0x200  /* DPlus Pullup enable */
#define DMINUS_PULLUP_EN                                     0x100  /* DMinus Pullup enable */
#define DPLUS_PULLDOWN_EN                                    0x80   /* DPlus Pulldown enable */
#define DMINUS_PULLDOWN_EN                                   0x40   /* DMinus Pulldown enable */
#define OTG_DATA_STAT                                        0x0004 /* TTL logic state of VBUS pin [R] */
#define OTG_ID_STAT                                          0x0002 /* Value of OTG ID pin [R] */
#define VBUS_VALID_FLG                                       0x0001 /* VBUS > 4.4V [R] */


/*********************************************************/
/*********************************************************/
/* GPIO REGISTERS                                        */
/*********************************************************/
/*********************************************************/

/*********************************************************/
/* GPIO CONTROL REGISTER [R/W]                           */
/*********************************************************/

#define GPIO_CTL_REG                                         0xC006 /* GPIO Control Register [R/W] */

/* FIELDS */
#define GPIO_WP_EN                                           0x8000 /* GPIO Control Register Write-Protect enable (1:WP) */
#define UD                                                   0x0400 /* Routes Port1A TX enable status to GPIO[30] */
#define GPIO_SAS_EN                                          0x0800 /* 1:SPI SS to GPIO[15] */
#define GPIO_MODE_SEL                                        0x0700 /* GPIO Mode       */
#define GPIO_HSS_EN                                          0x0080 /* Connect HSS to GPIO (Location depends on chip) */
/* EZ-Host: GPIO [26, 18:16] */
/* EZ-OTG: GPIO[15:12] */
#define GPIO_HSS_XD_EN                                       0x0040 /* Connect HSS to XD[15:12] (TQFP only) */
#define GPIO_SPI_EN                                          0x0020 /* Connect SPI to GPIO[11:8] */
#define GPIO_SPI_XD_EN                                       0x0010 /* Connect SPI to XD[11:8] */
#define GPIO_IRQ1_POL_SEL                                    0x0008 /* IRQ1 polarity (1:positive, 0:negative)  */
#define GPIO_IRQ1_EN                                         0x0004 /* IRQ1 enable */
#define GPIO_IRQ0_POL_SEL                                    0x0002 /* IRQ0 polarity (1:positive, 0:negative) */
#define GPIO_IRQ0_EN                                         0x0001 /* IRQ0 enable */

/* GPIO MODE FIELD VALUES */

#define SCAN_MODE                                            0x0006 /* Boundary Scan mode */
#define HPI_MODE                                             0x0005 /* HPI mode */
#define IDE_MODE                                             0x0004 /* IDE mode */
#define EPP_MODE                                             0x0002 /* EPP mode */
#define GPIO_MODE                                            0x0000 /* GPIO only */

/*********************************************************/
/* GPIO n REGISTERS                                      */
/*********************************************************/

#define GPIO0_OUT_DATA_REG                                   0xC01E /* GPIO 0 Output Data Register [R/W] */
#define GPIO1_OUT_DATA_REG                                   0xC024 /* GPIO 1 Output Data Register [R/W] */

#define GPIO0_IN_DATA_REG                                    0xC020 /* GPIO 0 Input Data Register [R] */
#define GPIO1_IN_DATA_REG                                    0xC026 /* GPIO 1 Input Data Register [R] */

#define GPIO0_DIR_REG                                        0xC022 /* GPIO 0 Direction Register [R/W] (1:Output, 0:Input) */
#define GPIO1_DIR_REG                                        0xC028 /* GPIO 1 Direction Register [R/W] (1:Output, 0:Input) */
#define GPIO_HI_IO                                           0xC024 /* Alias for BIOS */
#define GPIO_HI_ENB                                          0xC028 /* Alias for BIOS */

/*********************************************************/
/*********************************************************/
/* IDE REGISTERS                                         */
/*********************************************************/
/*********************************************************/

/*********************************************************/
/* IDE MODE REGISTER [R/W]                               */
/*********************************************************/

#define IDE_MODE_REG                                         0xC048 /* IDE Mode Register [R/W] */

/* FIELDS */

#define IDE_MODE_SEL                                         0x0007 /* IDE Mode (See field values below) */

/* MODE FIELD VALUES */

#define MODE_DIS                                             0x0007 /* Disabled */
#define MODE_PIO4                                            0x0004 /* PIO Mode 4 */
#define MODE_PIO3                                            0x0003 /* PIO Mode 3 */
#define MODE_PIO2                                            0x0002 /* PIO Mode 2 */
#define MODE_PIO1                                            0x0001 /* PIO Mode 1 */
#define MODE_PIO0                                            0x0000 /* PIO Mode 0 */

/*********************************************************/
/* IDE START ADDRESS REGISTER [R/W]                      */
/*********************************************************/

#define IDE_START_ADDR_REG                                   0xC04A /* IDE Start Address Register [R/W] */

/*********************************************************/
/* IDE STOP ADDRESS REGISTER [R/W]                       */
/*********************************************************/

#define IDE_STOP_ADDR_REG                                    0xC04C /* IDE Stop Address Register [R/W] */

/*********************************************************/
/* IDE CONTROL REGISTER [R/W]                            */
/*********************************************************/

#define IDE_CTL_REG                                          0xC04E /* IDE Control Register [R/W] */

/* FIELDS */

#define IDE_DIR_SEL                                          0x0008 /* IDE Direction Select */
#define IDE_IRQ_EN                                           0x0004 /* IDE Interrupt Enable */
#define IDE_DONE_FLG                                         0x0002 /* IDE Done F