cy7c67200_300.h

USB Host 资料

#define ERROR_FLG                                            0x0002 /* Error occurred */
#define ACK_FLG                                              0x0001 /* Transfer ACK'd        */

/*********************************************************/
/* HOST n DEVICE ADDRESS REGISTERS [W]                   */
/*********************************************************/

#define HOST1_DEV_ADDR_REG                                   0xC088 /* Host 1 Device Address Register [W] */
#define HOST2_DEV_ADDR_REG                                   0xC0A8 /* Host 2 Device Address Register [W] */


/* FIELDS */

#define DEV_ADDR                                             0x007F /* Device Address */

/*********************************************************/
/* HOST n COUNT RESULT REGISTERS [R]                     */
/*********************************************************/

#define HOST1_CTR_REG                                        0xC088 /* Host 1 Counter Register [R] */
#define HOST2_CTR_REG                                        0xC0A8 /* Host 2 Counter Register [R] */

/* FIELDS*/

#define HOST_RESULT                                          0x00FF /* Host Count Result */

/*********************************************************/
/* HOST n SOF/EOP COUNT REGISTER [R/W]                   */
/*********************************************************/

#define HOST1_SOF_EOP_CNT_REG                                0xC092 /* Host 1 SOF/EOP Count Register [R/W] */
#define HOST2_SOF_EOP_CNT_REG                                0xC0B2 /* Host 2 SOF/EOP Count Register [R/W] */


/* FIELDS */

#define SOF_EOP_CNT                                          0x3FFF /* SOF/EOP Count */

/*********************************************************/
/* HOST n SOF/EOP COUNTER REGISTER [R]                       */
/*********************************************************/

#define HOST1_SOF_EOP_CTR_REG                                0xC094 /* Host 1 SOF/EOP Counter Register [R] */
#define HOST2_SOF_EOP_CTR_REG                                0xC0B4 /* Host 2 SOF/EOP Counter Register [R] */


/* FIELDS */

#define SOF_EOP_CTR                                          0x3FFF /* SOF/EOP Counter */

/*********************************************************/
/* HOST n FRAME REGISTER [R]                             */
/*********************************************************/

#define HOST1_FRAME_REG                                      0xC096 /* Host 1 Frame Register [R] */
#define HOST2_FRAME_REG                                      0xC0B6 /* Host 2 Frame Register [R] */


/* FIELDS */

#define HOST_FRAME_NUM                                       0x07FF /* Frame */


/*********************************************************/
/*********************************************************/
/* DEVICE REGISTERS                                      */
/*********************************************************/
/*********************************************************/

/*********************************************************/
/* DEVICE n PORT SELECT REGISTERS [R/W]                  */
/*********************************************************/

#define DEV1_SEL_REG                                         0xC084 /* Device 1 Port Select Register [R/W] */
#define DEV2_SEL_REG                                         0xC0A4 /* Device 2 Port Select Register [R/W] */

/* FIELDS */

/*********************************************************/
/* DEVICE n INTERRUPT ENABLE REGISTER [R/W]              */
/*********************************************************/

#define DEV1_IRQ_EN_REG                                      0xC08C /* Device 1 Interrupt Enable Register [R/W] */
#define DEV2_IRQ_EN_REG                                      0xC0AC /* Device 2 Interrupt Enable Register [R/W] */

/* FIELDS */

#define SOF_EOP_TMOUT_IRQ_EN                                 0x0800 /* SOF/EOP Timeout Interrupt Enable */
/* Field name defined in Host Enable Register
 * #define DEV_SOF_EOP_IRQ_EN                                0x0200 /# SOF/EOP Interrupt Enable #/
 */
#define RST_IRQ_EN                                           0x0100 /* Reset Interrupt Enable */                    
#define EP7_IRQ_EN                                           0x0080 /* EP7 Interrupt Enable  */
#define EP6_IRQ_EN                                           0x0040 /* EP6 Interrupt Enable  */
#define EP5_IRQ_EN                                           0x0020 /* EP5 Interrupt Enable  */
#define EP4_IRQ_EN                                           0x0010 /* EP4 Interrupt Enable  */
#define EP3_IRQ_EN                                           0x0008 /* EP3 Interrupt Enable  */
#define EP2_IRQ_EN                                           0x0004 /* EP2 Interrupt Enable  */
#define EP1_IRQ_EN                                           0x0002 /* EP1 Interrupt Enable  */
#define EP0_IRQ_EN                                           0x0001 /* EP0 Interrupt Enable  */

/*********************************************************/
/* DEVICE n STATUS REGISTER [R/W]                        */
/*********************************************************/
/* In order to clear status for a particular IRQ bit,    */
/* write a '1' to that bit location.                     */
/*********************************************************/

#define DEV1_STAT_REG                                        0xC090 /* Device 1 Status Register [R/W] */
#define DEV2_STAT_REG                                        0xC0B0 /* Device 2 Status Register [R/W] */

/* FIELDS */

/* Defined in Host Status Register
 * #define VBUS_IRQ_FLG                                      0x8000 /# VBUS Interrupt Request (DEV1 only) #/
 * #define ID_IRQ_FLG                                        0x4000 /# ID Interrupt Request (DEV1 only) #/
 * #define SOF_EOP_IRQ_FLG                                   0x0200 /# SOF/EOP Interrupt Request #/
 */
#define RST_IRQ_FLG                                          0x0100 /* Reset Interrupt Request */
#define EP7_IRQ_FLG                                          0x0080 /* EP7 Interrupt Request */
#define EP6_IRQ_FLG                                          0x0040 /* EP6 Interrupt Request */
#define EP5_IRQ_FLG                                          0x0020 /* EP5 Interrupt Request */
#define EP4_IRQ_FLG                                          0x0010 /* EP4 Interrupt Request */
#define EP3_IRQ_FLG                                          0x0008 /* EP3 Interrupt Request */
#define EP2_IRQ_FLG                                          0x0004 /* EP2 Interrupt Request */
#define EP1_IRQ_FLG                                          0x0002 /* EP1 Interrupt Request */
#define EP0_IRQ_FLG                                          0x0001 /* EP0 Interrupt Request */

/*********************************************************/
/* DEVICE n ADDRESS REGISTERS [R/W]                      */
/*********************************************************/

#define DEV1_ADDR_REG                                        0xC08E /* Device 1 Address Register [R/W] */
#define DEV2_ADDR_REG                                        0xC0AE /* Device 2 Address Register [R/W] */

/* FIELDS */

#define DEV_ADDR_SEL                                         0x007F /* Device Address */

/*********************************************************/
/* DEVICE n FRAME NUMBER REGISTER [R]                    */
/*********************************************************/

#define DEV1_FRAME_REG                                       0xC092 /* Device 1 Frame Register [R] */
#define DEV2_FRAME_REG                                       0xC0B2 /* Device 2 Frame Register [R] */

/* FIELDS */

#define SOF_EOP_TMOUT_FLG                                    0x8000 /* SOF/EOP Timeout occured */
#define SOF_EOP_TMOUT_CNTR                                   0x7000 /* SOF/EOP Timeout Interrupt Counter */
#define DEV_FRAME_STAT                                       0x07FF /* Device Frame */

/*********************************************************/
/* DEVICE n ENDPOINT n CONTROL REGISTERS [R/W]           */
/*********************************************************/

#define DEV1_EP0_CTL_REG                                     0x0200 /* Device 1 Endpoint 0 Control Register [R/W] */
#define DEV1_EP1_CTL_REG                                     0x0210 /* Device 1 Endpoint 1 Control Register [R/W]       */
#define DEV1_EP2_CTL_REG                                     0x0220 /* Device 1 Endpoint 2 Control Register [R/W] */
#define DEV1_EP3_CTL_REG                                     0x0230 /* Device 1 Endpoint 3 Control Register [R/W] */
#define DEV1_EP4_CTL_REG                                     0x0240 /* Device 1 Endpoint 4 Control Register [R/W] */
#define DEV1_EP5_CTL_REG                                     0x0250 /* Device 1 Endpoint 5 Control Register [R/W] */
#define DEV1_EP6_CTL_REG                                     0x0260 /* Device 1 Endpoint 6 Control Register [R/W] */
#define DEV1_EP7_CTL_REG                                     0x0270 /* Device 1 Endpoint 7 Control Register [R/W] */

#define DEV2_EP0_CTL_REG                                     0x0280 /* Device 2 Endpoint 0 Control Register [R/W] */
#define DEV2_EP1_CTL_REG                                     0x0290 /* Device 2 Endpoint 1 Control Register [R/W]       */
#define DEV2_EP2_CTL_REG                                     0x02A0 /* Device 2 Endpoint 2 Control Register [R/W] */
#define DEV2_EP3_CTL_REG                                     0x02B0 /* Device 2 Endpoint 3 Control Register [R/W] */
#define DEV2_EP4_CTL_REG                                     0x02C0 /* Device 2 Endpoint 4 Control Register [R/W] */
#define DEV2_EP5_CTL_REG                                     0x02D0 /* Device 2 Endpoint 5 Control Register [R/W] */
#define DEV2_EP6_CTL_REG                                     0x02E0 /* Device 2 Endpoint 6 Control Register [R/W] */
#define DEV2_EP7_CTL_REG                                     0x02F0 /* Device 2 Endpoint 7 Control Register [R/W] */

#define SIE1_DEV_REQ                                         0x0300 /* SIE1 Default Setup packet Address */
#define SIE2_DEV_REQ                                         0x0308 /* SIE2 Default Setup packet Address */

/* FIELDS */

#define INOUT_IGN_EN                                         0x0080 /* Ignores IN and OUT requests on EP0     */
#define STALL_EN                                             0x0020 /* Endpoint Stall */
#define NAK_INT_EN                                           0x0080 /* NAK Response Interrupt enable  */

/*********************************************************/
/* DEVICE n ENDPOINT n ADDRESS REGISTERS [R/W]           */
/*********************************************************/

#define DEV1_EP0_ADDR_REG                                    0x0202 /* Device 1 Endpoint 0 Address Register [R/W] */
#define DEV1_EP1_ADDR_REG                                    0x0212 /* Device 1 Endpoint 1 Address Register [R/W]      */
#define DEV1_EP2_ADDR_REG                                    0x0222 /* Device 1 Endpoint 2 Address Register [R/W] */
#define DEV1_EP3_ADDR_REG                                    0x0232 /* Device 1 Endpoint 3 Address Register [R/W] */
#define DEV1_EP4_ADDR_REG                                    0x0242 /* Device 1 Endpoint 4 Address Register [R/W] */
#define DEV1_EP5_ADDR_REG                                    0x0252 /* Device 1 Endpoint 5 Address Register [R/W] */
#define DEV1_EP6_ADDR_REG                                    0x0262 /* Device 1 Endpoint 6 Address Register [R/W] */
#define DEV1_EP7_ADDR_REG                                    0x0272 /* Device 1 Endpoint 7 Address Register [R/W] */

#define DEV2_EP0_ADDR_REG                                    0x0282 /* Device 2 Endpoint 0 Address Register [R/W] */
#define DEV2_EP1_ADDR_REG                                    0x0292 /* Device 2 Endpoint 1 Address Register [R/W] */
#define DEV2_EP2_ADDR_REG                                    0x02A2 /* Device 2 Endpoint 2 Address Register [R/W] */
#define DEV2_EP3_ADDR_REG                                    0x02B2 /* Device 2 Endpoint 3 Address Register [R/W] */
#define DEV2_EP4_ADDR_REG                                    0x02C2 /* Device 2 Endpoint 4 Address Register [R/W] */
#define DEV2_EP5_ADDR_REG                                    0x02D2 /* Device 2 Endpoint 5 Address Register [R/W] */
#define DEV2_EP6_ADDR_REG                                    0x02E2 /* Device 2 Endpoint 6 Address Register [R/W] */
#define DEV2_EP7_ADDR_REG                                    0x02F2 /* Device 2 Endpoint 7 Address Register [R/W] */

/*********************************************************/
/* DEVICE n ENDPOINT n COUNT REGISTERS [R/W]             */
/*********************************************************/

#define DEV1_EP0_CNT_REG                                     0x0204 /* Device 1 Endpoint 0 Count Register [R/W] */
#define DEV1_EP1_CNT_REG                                     0x0214 /* Device 1 Endpoint 1 Count Register [R/W]       */
#define DEV1_EP2_CNT_REG                                     0x0224 /* Device 1 Endpoint 2 Count Register [R/W] */
#define DEV1_EP3_CNT_REG                                     0x0234 /* Device 1 Endpoint 3 Count Register [R/W] */