📄 cy7c67200_300.h
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/*********************************************************//* TIMER n REGISTER [R/W] *//*********************************************************/#define TMR0_REG 0xC010 /* Timer 0 Register [R/W] */#define TMR1_REG 0xC012 /* Timer 1 Register [R/W] *//*********************************************************//*********************************************************//* USB REGISTERS *//*********************************************************//*********************************************************//*********************************************************//* USB n CONTROL REGISTERS [R/W] *//*********************************************************/#define USB1_CTL_REG 0xC08A /* USB 1 Control Register [R/W] */#define USB2_CTL_REG 0xC0AA /* USB 2 Control Register [R/W] *//* FIELDS */#define B_DP_STAT 0x8000 /* Port B D+ status */#define B_DM_STAT 0x4000 /* Port B D- status */#define A_DP_STAT 0x2000 /* Port A D+ status */#define A_DM_STAT 0x1000 /* Port A D- status */#define B_SPEED_SEL 0x0800 /* Port B Speed select (See below) */#define A_SPEED_SEL 0x0400 /* Port A Speed select (See below) */#define MODE_SEL 0x0200 /* Mode (See below) */#define B_RES_EN 0x0100 /* Port B Resistors enable */#define A_RES_EN 0x0080 /* Port A Resistors enable */#define B_FORCE_SEL 0x0060 /* Port B Force D+/- state (See below) */#define A_FORCE_SEL 0x0018 /* Port A Force D+/- state (See below) */#define SUSP_EN 0x0004 /* Suspend enable */#define B_SOF_EOP_EN 0x0002 /* Port B SOF/EOP enable */#define A_SOF_EOP_EN 0x0001 /* Port A SOF/EOP enable *//* MODE FIELD VALUES */#define HOST_MODE 0x0200 /* Host mode */#define DEVICE_MODE 0x0000 /* Device mode *//* p_SPEED SELECT FIELD VALUES */#define LOW_SPEED 0xFFFF /* Low speed */#define FULL_SPEED 0x0000 /* Full speed */#define B_SPEED_LOW 0x0800#define B_SPEED_FULL 0x0000#define A_SPEED_LOW 0x0400#define A_SPEED_FULL 0x0000/* FORCEn FIELD VALUES */#define FORCE_K 0x0078 /* Force K state on associated port */#define FORCE_SE0 0x0050 /* Force SE0 state on associated port */#define FORCE_J 0x0028 /* Force J state on associated port */#define FORCE_NORMAL 0x0000 /* Don't force associated port */#define A_FORCE_K 0x0018 /* Force K state on A port */#define A_FORCE_SE0 0x0010 /* Force SE0 state on associated port */#define A_FORCE_J 0x0008 /* Force J state on associated port */#define A_FORCE_NORMAL 0x0000 /* Don't force associated port */#define B_FORCE_K 0x0060 /* Force K state on associated port */#define B_FORCE_SE0 0x0040 /* Force SE0 state on associated port */#define B_FORCE_J 0x0020 /* Force J state on associated port */#define B_FORCE_NORMAL 0x0000 /* Don't force associated port *//*********************************************************//*********************************************************//* HOST REGISTERS *//*********************************************************//*********************************************************//*********************************************************//* HOST n INTERRUPT ENABLE REGISTER [R/W] *//*********************************************************/#define HOST1_IRQ_EN_REG 0xC08C /* Host 1 Interrupt Enable Register [R/W] */ #define HOST2_IRQ_EN_REG 0xC0AC /* Host 2 Interrupt Enable Register [R/W] *//* FIELDS */#define VBUS_IRQ_EN 0x8000 /* VBUS Interrupt Enable (Available on HOST1 only) */#define ID_IRQ_EN 0x4000 /* ID Interrupt Enable (Available on HOST1 only) */#define SOF_EOP_IRQ_EN 0x0200 /* SOF/EOP Interrupt Enable */#define B_WAKE_IRQ_EN 0x0080 /* Port B Wake Interrupt Enable */#define A_WAKE_IRQ_EN 0x0040 /* Port A Wake Interrupt Enable */#define B_CHG_IRQ_EN 0x0020 /* Port B Connect Change Interrupt Enable */#define A_CHG_IRQ_EN 0x0010 /* Port A Connect Change Interrupt Enable */#define DONE_IRQ_EN 0x0001 /* Done Interrupt Enable *//*********************************************************//* HOST n STATUS REGISTER [R/W] *//*********************************************************//* In order to clear status for a particular IRQ bit, *//* write a '1' to that bit location. *//*********************************************************/#define HOST1_STAT_REG 0xC090 /* Host 1 Status Register [R/W] */#define HOST2_STAT_REG 0xC0B0 /* Host 2 Status Register [R/W] *//* FIELDS */#define VBUS_IRQ_FLG 0x8000 /* VBUS Interrupt Request (HOST1 only) */#define ID_IRQ_FLG 0x4000 /* ID Interrupt Request (HOST1 only) */#define SOF_EOP_IRQ_FLG 0x0200 /* SOF/EOP Interrupt Request */#define B_WAKE_IRQ_FLG 0x0080 /* Port B Wake Interrupt Request */#define A_WAKE_IRQ_FLG 0x0040 /* Port A Wake Interrupt Request */#define B_CHG_IRQ_FLG 0x0020 /* Port B Connect Change Interrupt Request */#define A_CHG_IRQ_FLG 0x0010 /* Port A Connect Change Interrupt Request */#define B_SE0_STAT 0x0008 /* Port B SE0 status */#define A_SE0_STAT 0x0004 /* Port A SE0 status */#define DONE_IRQ_FLG 0x0001 /* Done Interrupt Request *//*********************************************************//* HOST n CONTROL REGISTERS [R/W] *//*********************************************************/#define HOST1_CTL_REG 0xC080 /* Host 1 Control Register [R/W] */#define HOST2_CTL_REG 0xC0A0 /* Host 2 Control Register [R/W] *//* FIELDS */#define PREAMBLE_EN 0x0080 /* Preamble enable */#define SEQ_SEL 0x0040 /* Data Toggle Sequence Bit Select (Write next/read last) */#define SYNC_EN 0x0020 /* (1:Send next packet at SOF/EOP, 0: Send next packet immediately) */#define ISO_EN 0x0010 /* Isochronous enable */#define ARM_EN 0x0001 /* Arm operation */#define BSY_FLG 0x0001 /* Busy flag *//*********************************************************//* HOST n ADDRESS REGISTERS [R/W] *//*********************************************************/#define HOST1_ADDR_REG 0xC082 /* Host 1 Address Register [R/W] */#define HOST2_ADDR_REG 0xC0A2 /* Host 2 Address Register [R/W] *//*********************************************************//* HOST n COUNT REGISTERS [R/W] *//*********************************************************/#define HOST1_CNT_REG 0xC084 /* Host 1 Count Register [R/W] */#define HOST2_CNT_REG 0xC0A4 /* Host 2 Count Register [R/W] *//* FIELDS */#define PORT_SEL 0x4000 /* Port Select (1:PortB, 0:PortA) */#define HOST_CNT 0x03FF /* Host Count *//*********************************************************//* HOST n PID REGISTERS [W] *//*********************************************************/#define HOST1_PID_REG 0xC086 /* Host 1 PID Register [W] */#define HOST2_PID_REG 0xC0A6 /* Host 2 PID Register [W] *//* FIELDS */#define PID_SEL 0x00F0 /* Packet ID (see below) */#define EP_SEL 0x000F /* Endpoint number *//* PID FIELD VALUES */#define SETUP_PID 0x000D /* SETUP */#define IN_PID 0x0009 /* IN */#define OUT_PID 0x0001 /* OUT */#define SOF_PID 0x0005 /* SOF */#define PRE_PID 0x000C /* PRE */#define NAK_PID 0x000A /* NAK */#define STALL_PID 0x000E /* STALL */#define DATA0_PID 0x0003 /* DATA0 */#define DATA1_PID 0x000B /* DATA1 *//*********************************************************//* OTG-Host Define value *//*********************************************************/#define PortA 0x0000#define PortB 0x0001#define PortC 0x0002#define PortD 0x0003#define PID_SETUP 0x000D#define PID_IN 0x0009#define PID_OUT 0x0001#define PID_SOF 0x0005#define PID_PRE 0x000C#define PID_NAK 0x000A#define PID_STALL 0x000E#define PID_DATA0 0x0003#define PID_DATA1 0x000B#define PID_ACK 0x0002/*********************************************************//* HOST n ENDPOINT STATUS REGISTERS [R] *//*********************************************************/#define HOST1_EP_STAT_REG 0xC086 /* Host 1 Endpoint Status Register [R] */#define HOST2_EP_STAT_REG 0xC0A6 /* Host 2 Endpoint Status Register [R] *//* FIELDS */#define OVERFLOW_FLG 0x0800 /* Receive overflow */#define UNDERFLOW_FLG 0x0400 /* Receive underflow */#define STALL_FLG 0x0080 /* Device returned STALL */#define NAK_FLG 0x0040 /* Device returned NAK */#define LENGTH_EXCEPT_FLG 0x0020 /* Overflow or Underflow occured */#define SEQ_STAT 0x0008 /* Data Toggle value */#define TIMEOUT_FLG 0x0004 /* Timeout occurred */⌨️ 快捷键说明
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