📄 cy7c67200_300.h
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/* HPI_STAT_PORT *//* *//*********************************************************//*********************************************************//*********************************************************//* CPU REGISTERS *//*********************************************************//*********************************************************//*********************************************************//* CPU FLAGS REGISTER [R] *//*********************************************************/#define CPU_FLAGS_REG 0xC000 /* CPU Flags Register [R] *//* FIELDS */#define GLOBAL_IRQ_EN 0x0010 /* Global Interrupt Enable */#define NEG_FLG 0x0008 /* Negative Sign Flag */#define OVF_FLG 0x0004 /* Overflow Flag */#define CARRY_FLG 0x0002 /* Carry/Borrow Flag */#define ZER0_FLG 0x0001 /* Zero Flag *//*********************************************************//* BANK REGISTER [R/W] *//*********************************************************/#define BANK_REG 0xC002 /* Bank Register [R/W] */#define BANK 0xFFE0 /* Bank *//*********************************************************//* HARDWARE REVISION REGISTER [R] *//*********************************************************//* First Silicon Revision is 0x0101. Revision number *//* will be incremented by one for each revision change. *//*********************************************************/#define HW_REV_REG 0xC004 /* Hardware Revision Register [R] *//*********************************************************//* INTERRUPT ENABLE REGISTER [R/W] *//*********************************************************/#define IRQ_EN_REG 0xC00E /* Interrupt Enable Register [R/W] *//* FIELDS */#define OTG_IRQ_EN 0x1000 /* OTG Interrupt Enable */#define SPI_IRQ_EN 0x0800 /* SPI Interrupt Enable */#define HOST2_IRQ_EN 0x0200 /* Host 2 Interrupt Enable */#define DEV2_IRQ_EN 0x0200 /* Device 2 Interrupt Enable */#define HOST1_IRQ_EN 0x0100 /* Host 1 Interrupt Enable */#define DEV1_IRQ_EN 0x0100 /* Device 1 Interrupt Enable */#define HSS_IRQ_EN 0x0080 /* HSS Interrupt Enable */#define IN_MBX_IRQ_EN 0x0040 /* In Mailbox Interrupt Enable */#define OUT_MBX_IRQ_EN 0x0020 /* Out Mailbox Interrupt Enable */#define UART_IRQ_EN 0x0008 /* UART Interrupt Enable */#define GPIO_IRQ_EN 0x0004 /* GPIO Interrupt Enable */#define TMR1_IRQ_EN 0x0002 /* Timer 1 Interrupt Enable */#define TMR0_IRQ_EN 0x0001 /* Timer 0 Interrupt Enable *//*********************************************************//* CPU SPEED REGISTER [R/W] *//*********************************************************/#define CPU_SPEED_REG 0xC008 /* CPU Speed Register [R/W] *//* CPU SPEED REGISTER FIELDS **** The Speed field in the CPU Speed Register provides a mechanism to** divide the external clock signal down to operate the CPU at a lower ** clock speed (presumedly for lower-power operation). The value loaded ** into this field is a divisor and is calculated as (n+1). For instance, ** if 3 is loaded into the field, the resulting CPU speed will be PCLK/4.*/#define CPU_SPEED 0x000F /* CPU Speed *//*********************************************************//* POWER CONTROL REGISTER [R/W] *//*********************************************************/#define POWER_CTL_REG 0xC00A /* Power Control Register [R/W] *//* FIELDS */#define HOST2B_WAKE_EN 0x8000 /* Host 2B Wake Enable */#define DEV2B_WAKE_EN 0x8000 /* Device 2B Wake Enable */#define HOST2A_WAKE_EN 0x4000 /* Host 2A Wake Enable */#define DEV2A_WAKE_EN 0x4000 /* Device 2A Wake Enable */#define HOST1B_WAKE_EN 0x2000 /* Host 1B Wake Enable */#define DEV1B_WAKE_EN 0x2000 /* Device 1B Wake Enable */#define HOST1A_WAKE_EN 0x1000 /* Host 1A Wake Enable */#define DEV1A_WAKE_EN 0x1000 /* Device 1A Wake Enable */#define OTG_WAKE_EN 0x0800 /* OTG Wake Enable */#define HSS_WAKE_EN 0x0200 /* HSS Wake Enable */#define SPI_WAKE_EN 0x0100 /* SPI Wake Enable */#define HPI_WAKE_EN 0x0080 /* HPI Wake Enable */#define GPIO_WAKE_EN 0x0010 /* GPIO Wake Enable */#define BOOST_OK_FLG 0x0004 /* Boost 3V OK Flag */#define SLEEP_EN 0x0002 /* Sleep Enable */#define HALT_EN 0x0001 /* Halt Enable *//*********************************************************//* BREAKPOINT REGISTER [R/W] *//*********************************************************/#define BKPT_REG 0xC014 /* Breakpoint Register [R/W] *//*********************************************************//* USB DIAGNOSTIC REGISTER [W] *//*********************************************************/#define USB_DIAG_REG 0xC03C /* USB Diagnostic Register [R/W] *//* FIELDS */#define c2B_DIAG_EN 0x8000 /* Port 2B Diagnostic Enable */#define c2A_DIAG_EN 0x4000 /* Port 2A Diagnostic Enable */#define c1B_DIAG_EN 0x2000 /* Port 1B Diagnostic Enable */#define c1A_DIAG_EN 0x1000 /* Port 1A Diagnostic Enable */#define PULLDOWN_EN 0x0040 /* Pull-down resistors enable */#define LS_PULLUP_EN 0x0020 /* Low-speed pull-up resistor enable */#define FS_PULLUP_EN 0x0010 /* Full-speed pull-up resistor enable */#define FORCE_SEL 0x0007 /* Control D+/- lines *//* FORCE FIELD VALUES */#define ASSERT_SE0 0x0004 /* Assert SE0 on selected ports */#define TOGGLE_JK 0x0002 /* Toggle JK state on selected ports */#define ASSERT_J 0x0001 /* Assert J state on selected ports */#define ASSERT_K 0x0000 /* Assert K state on selected ports *//*********************************************************//* MEMORY DIAGNOSTIC REGISTER [W] *//*********************************************************/#define MEM_DIAG_REG 0xC03E /* Memory Diagnostic Register [W] *//* FIELDS */#define MEM_ARB_SEL 0x0700 /* Memory Arbitration */#define MONITOR_EN 0x0001 /* Monitor Enable (Echoes internal address bus externally) *//* MEMORY ARBITRATION SELECT FIELD VALUES */#define MEM_ARB_7 0x0700 /* Number of dead cycles out of 8 possible */#define MEM_ARB_6 0x0600 /* Should not use any cycle >= 6 */#define MEM_ARB_5 0x0500 /* */#define MEM_ARB_4 0x0400 /* */#define MEM_ARB_3 0x0300 /* */#define MEM_ARB_2 0x0200 /* */#define MEM_ARB_1 0x0100 /* */#define MEM_ARB_0 0x0000 /* Power up default *//*********************************************************//* EXTENDED PAGE n MAP REGISTER [R/W] *//*********************************************************/#define PG1_MAP_REG 0xC018 /* Page 1 Map Register [R/W] */#define PG2_MAP_REG 0xC01A /* Page 2 Map Register [R/W] *//*********************************************************//* EXTERNAL MEMORY CONTROL REGISTER [R/W] *//*********************************************************/#define XMEM_CTL_REG 0xC03A /* External Memory Control Register [R/W] *//* FIELDS */#define XRAM_MERGE_EN 0x2000 /* Overlay XRAMSEL w/ XMEMSEL */#define XROM_MERGE_EN 0x1000 /* Overlay XROMSEL w/ XMEMSEL */#define XMEM_WIDTH_SEL 0x0800 /* External MEM Width Select */#define XMEM_WAIT_SEL 0x0700 /* Number of Extended Memory wait states (0-7) */#define XROM_WIDTH_SEL 0x0080 /* External ROM Width Select */#define XROM_WAIT_SEL 0x0070 /* Number of External ROM wait states (0-7) */#define XRAM_WIDTH_SEL 0x0008 /* External RAM Width Select */#define XRAM_WAIT_SEL 0x0007 /* Number of External RAM wait states (0-7) *//* XMEM_WIDTH FIELD VALUES */#define XMEM_8 0x0800 /* */#define XMEM_16 0x0000 /* *//* XRAM_WIDTH FIELD VALUES */#define XROM_8 0x0080 /* */#define XROM_16 0x0000 /* *//* XRAM_WIDTH FIELD VALUES */#define XRAM_8 0x0008 /* */#define XRAM_16 0x0000 /* *//*********************************************************//* WATCHDOG TIMER REGISTER [R/W] *//*********************************************************/#define WDT_REG 0xC00C /* Watchdog Timer Register [R/W] *//* FIELDS */#define WDT_TIMEOUT_FLG 0x0020 /* WDT timeout flag */#define WDT_PERIOD_SEL 0x0018 /* WDT period select (options below) */#define WDT_LOCK_EN 0x0004 /* WDT enable */#define WDT_EN 0x0002 /* WDT lock enable */#define WDT_RST_STB 0x0001 /* WDT reset Strobe *//* WATCHDOG PERIOD FIELD VALUES */#define WDT_66MS 0x0003 /* 66.0 ms */#define WDT_22MS 0x0002 /* 22.0 ms */#define WDT_5MS 0x0001 /* 5.5 ms */#define WDT_1MS 0x0000 /* 1.4 ms */⌨️ 快捷键说明
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