sim.c

TI的DSP C55X的应用程序

/*                      Viterbi decode cc0[] & cc1[] bits into cl1[]    */
/*                          bit array.                                  */
/*                                                                      */
/*                      Extract VSELP parameters (including CRC) from   */
/*                          cl1[] and cl2[] bits. Dump these bits to    */
/*                          file "cltxbits.out".                        */
/*                                                                      */
/*                      Re-generate CRC and verify that it is identical */
/*                          to that extracted above. If it is not,      */
/*                          restore VSELP parameters from the last      */
/*                          valid frame and attenuate R0 accordingly.   */
/*                                                                      */
/*                      Dump VSELP parameters to file "is54sim.out"     */
/*                  }                                                   */
/*                                                                      */
/*                  If the receive CRC is valid, compare the raw tx     */
/*                      slot bits (in "tx_slot") to the raw rx slot     */
/*                      bits (in "rx_slot") and update BERR counters.   */
/*                                                                      */
/*                  Update and print Frame Number                       */
/*                                                                      */
/*              [END OF MAIN LOOP]                                      */
/*                                                                      */
/*              Display BERR for the raw slot bits calculated during    */
/*                  the simulation.                                     */
/*                                                                      */
/*                                                                      */
/*                  De-Allocate Memory for data buffers                 */
/*                                                                      */
/*                                                                      */
/* Inputs :                                                             */
/*          NONE  (input from files, see below)                         */
/*                                                                      */
/* Outputs :                                                            */
/*          NONE  (output to files, see below)                          */
/*                                                                      */
/* Data :                                                               */
/*                                                                      */
/*  spinput         : Name of input speech file,                        */
/*                                                                      */
/*  vselp           : Array of VSELP_SIZE elements containing VSELP     */
/*                    parameters. (see vselp.h)                         */
/*                                                                      */
/*  frame_num       : Current frame number in process.                  */
/*                                                                      */
/*  crc_error_state : Current CRC error state. This represents the      */
/*                    current number of consecutive CRC invalid frames. */
/*                    (0-7)                                             */
/*                                                                      */
/*  SNR             : Signal to Noise Ration dB                         */
/*                                                                      */
/*  v_speed         : Vehicle speed, in MPH                             */
/*                                                                      */
/*  Fc              : Carrier frequency, in MHZ                         */
/*                                                                      */
/*  sync2           : Sync word from slot #2. This is placed at the     */
/*                    end of the transmit slot built for continuity.    */
/*                                                                      */
/*  I_SRC           : Vector of in-phase component of PI/4 DQPSK        */
/*                    encoded data at 4X symbol rate. This              */
/*                    representation is used before, during and after   */
/*                    multipath fading and noise corruption. This       */
/*                    represents post-filtered transmit data and        */
/*                    pre-filtered receive data.                        */
/*                                                                      */
/*  Q_SRC           : Vector of quadrature component of PI/4 DQPSK      */
/*                    encoded data at 4X symbol rate. This              */
/*                    representation is used before, during and after   */
/*                    multipath fading and noise corruption. This       */
/*                    represents post-filtered transmit data and        */
/*                    pre-filtered receive data.                        */
/*                                                                      */
/*  out_I           : Vector of in-phase component of PI/4 DQPSK        */
/*                    encoded data at 1X symbol rate. This represents   */
/*                    pre-filtered transmit data and post-filtered      */
/*                    receive data.                                     */
/*                                                                      */
/*  out_Q           : Vector of in-phase component of PI/4 DQPSK        */
/*                    encoded data at 1X symbol rate. This represents   */
/*                    pre-filtered transmit data and post-filtered      */
/*                    receive data.                                     */
/*                                                                      */
/*  filt4           : 48-tap SRC filter (same as above, except that     */
/*                    all taps are divided by 4) used in receive        */
/*                    data filtering (rx_src() & sync_cor())            */
/*                                                                      */
/*  tx_filt         : 48-tap (4x12) SRC filter used in the transmit     */
/*                    data filtering process (tx_src()). Filter         */
/*                    parameters are permutated from "filt".            */
/*                                                                      */
/*  cl1             : Class 1 bit array (89 elements)                   */
/*                                                                      */
/*  cl2             : Class 2 bit array (82 elements)                   */
/*                                                                      */
/*  cc0             : cc0[] bit stream generated to/from cl1[] bits     */
/*                    during convolutional encoding/decoding int the    */
/*                    transmit/receive process.  (89 elements)          */
/*                                                                      */
/*  cc1             : cc1[] bit stream generated to/from cl1[] bits     */
/*                    during convolutional encoding/decoding int the    */
/*                    transmit/receive process.  (89 elements)          */
/*                                                                      */
/*  tx_data         : Pre-interleaved transmit slot data (260-element)  */
/*                                                                      */
/*  tx_idata        : Interleaved transmit slot data (260-element)      */
/*                                                                      */
/*  tx_slot         : Transmit slot (384 elements) consisting of 324    */
/*                    standard slot#1 bits surrounded with 32 zeroes    */
/*                    at the start and 28 sync word #2 bits at the end. */
/*                                                                      */
/*  rx_data         : De-Interleaved receive slot data (260-element)    */
/*                                                                      */
/*  rx_idata        : Interleaved (pre-deinterleaved) received slot     */
/*                    data (260-element).                               */
/*                                                                      */
/*  rx_slot         : Recovered receive slot (324-element)              */
/*                                                                      */
/*  alloc_list      : Array of MEM_STRUCT structures used in call       */
/*                    to memory() which allocates/de-allocates buffer   */
/*                    space used.                                       */
/*                                                                      */
/*                                                                      */
/************************************************************************/

void main()
{
    unsigned            vselp[VSELP_SIZE];
    int                 i, j, n, done, frame_num, crc_error_state;
    unsigned sync2[28]= {1,0,1,0,1,0,0,1,1,1,0,1,0,0,0,1,0,0,1,0,
                         0,1,1,1,1,0,1,0};
                
/* Allocated Array Section */ 

        /* Note pointers must be static (ANSI)                */
        /* Static locals enforce data hiding from other files */
        
    static unsigned    cl1[89], cl2[82], cc0[89], cc1[89],
                       tx_data[260], tx_idata[260], tx_slot[384], 
                       rx_data[260], rx_idata[260], rx_slot[324];

    static float       cap_t;  
    static int         Sc_fact;
    static int         out_I[193], out_Q[193], I_SRC[750], Q_SRC[750];
	
/*********************************************/
/* Pack end of tx slot with sync word for    */
/* slot #2.                                  */
/*********************************************/
    
    for( i = 0; i < 28;  i++ )  
    	tx_slot[i+356] = sync2[i];

/*********************************************/
/* Initialize State                          */
/*********************************************/

    frame_num       = 0;        /* Start with Frame #0  */
    crc_error_state = 0;        /* CRC Error State = 0  */
    done            = NO;       /* While Loop Exit Flag */

/*********************************************/
/* Initialize Interleave Data                */
/*********************************************/

    interleave_init();

/*********************************************/
/* Initialize Jack's channel model           */
/*********************************************/

    cap_t = jkch_init(v_speed,Fc, 4);
                               
/*********************************************/
/* Initialize noise model                    */
/*********************************************/
                               
	Sc_fact= noise_init(SNR);
                               
/*********************************************/
/* Initialize BER Reporting                  */
/* (This will clear counters)                */
/*********************************************/

    berr_count( tx_slot+32, rx_slot, crc_error_state, BERR_INIT );
    
/*********************************************/
/*  MAIN LOOP                                */
/*                                           */
/*  We will remain in this loop until        */
/*  the input speech file has been           */
/*  completely read.                         */
/*********************************************/

    n = 0;
    while( done == NO )
    {
        vselpin( spinput, vselp );                  /* Read input VSELP */

        if(n++ < DATALEN-1)
        {   
            crcgen( vselp );                        /* Generate CRC from VSELP parameters */
            
            get_cl1_cl2( cl1, cl2, vselp );         /* Obtain cl1[] and cl2[] bits from VSELP */

            convenc(cc0,cc1,cl1);                   /* encode array cl1 into arrays cc0 and cc1 */
        } 
        else
            done = YES; 

        build_slot_data( cl2, cc0, cc1, tx_data );  /* build slot data from cl2[], cc0[] & cc1[] */
        
        interleave( tx_data, tx_idata );            /* interleave tx slot data */
        
        build_slot( tx_idata, tx_slot+32 );         /* bullt tx slot with interleaved data */
       
        diffenc( tx_slot, out_I, out_Q);            /* differentially encode current frame */