top.vhf

51单片机C语言常用模块与综合系统设计实例精讲

      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             I4 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND5B1 : component is "BLACK_BOX";
   
   component AND5
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             I4 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND5 : component is "BLACK_BOX";
   
   component AND5B4
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             I4 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND5B4 : component is "BLACK_BOX";
   
begin
   I_36_53 : AND5B3
      port map (I0=>A0,
                I1=>A1,
                I2=>A2,
                I3=>A3,
                I4=>E,
                O=>D8);
   
   I_36_54 : AND5B2
      port map (I0=>A1,
                I1=>A2,
                I2=>E,
                I3=>A3,
                I4=>A0,
                O=>D9);
   
   I_36_55 : AND5B2
      port map (I0=>A0,
                I1=>A2,
                I2=>E,
                I3=>A3,
                I4=>A1,
                O=>D10);
   
   I_36_56 : AND5B1
      port map (I0=>A2,
                I1=>A0,
                I2=>A1,
                I3=>A3,
                I4=>E,
                O=>D11);
   
   I_36_57 : AND5B2
      port map (I0=>A0,
                I1=>A1,
                I2=>E,
                I3=>A3,
                I4=>A2,
                O=>D12);
   
   I_36_58 : AND5B1
      port map (I0=>A1,
                I1=>A0,
                I2=>A2,
                I3=>A3,
                I4=>E,
                O=>D13);
   
   I_36_59 : AND5B1
      port map (I0=>A0,
                I1=>A1,
                I2=>A2,
                I3=>A3,
                I4=>E,
                O=>D14);
   
   I_36_60 : AND5
      port map (I0=>A3,
                I1=>A2,
                I2=>A1,
                I3=>A0,
                I4=>E,
                O=>D15);
   
   I_36_61 : AND5B2
      port map (I0=>A3,
                I1=>A0,
                I2=>E,
                I3=>A2,
                I4=>A1,
                O=>D6);
   
   I_36_62 : AND5B1
      port map (I0=>A3,
                I1=>A2,
                I2=>A1,
                I3=>A0,
                I4=>E,
                O=>D7);
   
   I_36_63 : AND5B2
      port map (I0=>A3,
                I1=>A1,
                I2=>E,
                I3=>A2,
                I4=>A0,
                O=>D5);
   
   I_36_64 : AND5B3
      port map (I0=>A0,
                I1=>A1,
                I2=>A3,
                I3=>A2,
                I4=>E,
                O=>D4);
   
   I_36_65 : AND5B2
      port map (I0=>A2,
                I1=>A3,
                I2=>E,
                I3=>A0,
                I4=>A1,
                O=>D3);
   
   I_36_66 : AND5B3
      port map (I0=>A0,
                I1=>A3,
                I2=>A2,
                I3=>A1,
                I4=>E,
                O=>D2);
   
   I_36_67 : AND5B3
      port map (I0=>A1,
                I1=>A2,
                I2=>A3,
                I3=>A0,
                I4=>E,
                O=>D1);
   
   I_36_68 : AND5B4
      port map (I0=>A3,
                I1=>A2,
                I2=>A1,
                I3=>A0,
                I4=>E,
                O=>D0);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity top is
   port ( ADDR  : in    std_logic_vector (15 downto 0); 
          KEY   : in    std_logic_vector (7 downto 0); 
          RD    : in    std_logic; 
          RST   : in    std_logic; 
          WR    : in    std_logic; 
          ADCS  : out   std_logic; 
          DACS  : out   std_logic; 
          GPIOC : out   std_logic_vector (7 downto 0); 
          GPIOD : out   std_logic_vector (7 downto 0); 
          LED   : out   std_logic; 
          DATA  : inout std_logic_vector (7 downto 0));
end top;

architecture BEHAVIORAL of top is
   attribute BOX_TYPE   : string ;
   attribute HU_SET     : string ;
   signal CS0      : std_logic;
   signal CS1      : std_logic;
   signal CS2      : std_logic;
   signal CS3      : std_logic;
   signal CS4      : std_logic;
   signal CS5      : std_logic;
   signal CS6      : std_logic;
   signal CS7      : std_logic;
   signal CS8      : std_logic;
   signal CS9      : std_logic;
   signal CS10     : std_logic;
   signal CS11     : std_logic;
   signal CS12     : std_logic;
   signal CS13     : std_logic;
   signal CS14     : std_logic;
   signal CS15     : std_logic;
   signal DIN      : std_logic_vector (7 downto 0);
   signal DOUT     : std_logic_vector (7 downto 0);
   signal GPIOA    : std_logic_vector (7 downto 0);
   signal GPIOB    : std_logic_vector (7 downto 0);
   signal XLXN_25  : std_logic;
   signal XLXN_199 : std_logic;
   signal XLXN_206 : std_logic;
   signal XLXN_271 : std_logic;
   signal XLXN_303 : std_logic;
   component FDCE
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
   component IBUF8_MXILINX_top
      port ( I : in    std_logic_vector (7 downto 0); 
             O : out   std_logic_vector (7 downto 0));
   end component;
   
   component OBUFE8_MXILINX_top
      port ( E : in    std_logic; 
             I : in    std_logic_vector (7 downto 0); 
             O : out   std_logic_vector (7 downto 0));
   end component;
   
   component D4_16E_MXILINX_top
      port ( A0  : in    std_logic; 
             A1  : in    std_logic; 
             A2  : in    std_logic; 
             A3  : in    std_logic; 
             E   : in    std_logic; 
             D0  : out   std_logic; 
             D1  : out   std_logic; 
             D10 : out   std_logic; 
             D11 : out   std_logic; 
             D12 : out   std_logic; 
             D13 : out   std_logic; 
             D14 : out   std_logic; 
             D15 : out   std_logic; 
             D2  : out   std_logic; 
             D3  : out   std_logic; 
             D4  : out   std_logic; 
             D5  : out   std_logic; 
             D6  : out   std_logic; 
             D7  : out   std_logic; 
             D8  : out   std_logic; 
             D9  : out   std_logic);
   end component;
   
   component BUFT8_MXILINX_top
      port ( I : in    std_logic_vector (7 downto 0); 
             T : in    std_logic; 
             O : out   std_logic_vector (7 downto 0));
   end component;
   
   component INV
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : component is "BLACK_BOX";
   
   component FD8CE_MXILINX_top
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic_vector (7 downto 0); 
             Q   : out   std_logic_vector (7 downto 0));
   end component;
   
   component BUF
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of BUF : component is "BLACK_BOX";
   
   component OR3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR3 : component is "BLACK_BOX";
   
   component AND2B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
   
   attribute HU_SET of XLXI_5 : label is "XLXI_5_15";
   attribute HU_SET of XLXI_6 : label is "XLXI_6_14";
   attribute HU_SET of XLXI_69 : label is "XLXI_69_8";
   attribute HU_SET of XLXI_70 : label is "XLXI_70_9";
   attribute HU_SET of XLXI_76 : label is "XLXI_76_10";
   attribute HU_SET of XLXI_97 : label is "XLXI_97_11";
   attribute HU_SET of XLXI_101 : label is "XLXI_101_12";
   attribute HU_SET of XLXI_102 : label is "XLXI_102_13";
begin
   XLXI_3 : FDCE
      port map (C=>WR,
                CE=>CS2,
                CLR=>RST,
                D=>DIN(0),
                Q=>LED);
   
   XLXI_5 : IBUF8_MXILINX_top
      port map (I(7 downto 0)=>DATA(7 downto 0),
                O(7 downto 0)=>DIN(7 downto 0));
   
   XLXI_6 : OBUFE8_MXILINX_top
      port map (E=>XLXN_25,
                I(7 downto 0)=>DOUT(7 downto 0),
                O(7 downto 0)=>DATA(7 downto 0));
   
   XLXI_69 : D4_16E_MXILINX_top
      port map (A0=>ADDR(0),
                A1=>ADDR(1),
                A2=>ADDR(2),
                A3=>ADDR(3),
                E=>ADDR(15),
                D0=>CS0,
                D1=>CS1,
                D2=>CS2,
                D3=>CS3,
                D4=>CS4,
                D5=>CS5,
                D6=>CS6,
                D7=>CS7,
                D8=>CS8,
                D9=>CS9,
                D10=>CS10,
                D11=>CS11,
                D12=>CS12,
                D13=>CS13,
                D14=>CS14,
                D15=>CS15);
   
   XLXI_70 : BUFT8_MXILINX_top
      port map (I(7 downto 0)=>KEY(7 downto 0),
                T=>XLXN_199,
                O(7 downto 0)=>DOUT(7 downto 0));
   
   XLXI_71 : INV
      port map (I=>CS3,
                O=>XLXN_199);
   
   XLXI_76 : BUFT8_MXILINX_top
      port map (I(7 downto 0)=>GPIOA(7 downto 0),
                T=>XLXN_206,
                O(7 downto 0)=>DOUT(7 downto 0));
   
   XLXI_77 : INV
      port map (I=>CS11,
                O=>XLXN_206);
   
   XLXI_97 : BUFT8_MXILINX_top
      port map (I(7 downto 0)=>GPIOB(7 downto 0),
                T=>XLXN_271,
                O(7 downto 0)=>DOUT(7 downto 0));
   
   XLXI_98 : INV
      port map (I=>CS12,
                O=>XLXN_271);
   
   XLXI_101 : FD8CE_MXILINX_top
      port map (C=>WR,
                CE=>CS13,
                CLR=>RST,
                D(7 downto 0)=>DIN(7 downto 0),
                Q(7 downto 0)=>GPIOC(7 downto 0));
   
   XLXI_102 : FD8CE_MXILINX_top
      port map (C=>WR,
                CE=>CS14,
                CLR=>RST,
                D(7 downto 0)=>DIN(7 downto 0),
                Q(7 downto 0)=>GPIOD(7 downto 0));
   
   XLXI_104 : BUF
      port map (I=>CS0,
                O=>DACS);
   
   XLXI_105 : BUF
      port map (I=>CS1,
                O=>ADCS);
   
   XLXI_106 : OR3
      port map (I0=>CS3,
                I1=>CS11,
                I2=>CS12,
                O=>XLXN_303);
   
   XLXI_107 : AND2B1
      port map (I0=>RD,
                I1=>XLXN_303,
                O=>XLXN_25);
   
end BEHAVIORAL;