txmit.vhd

51单片机C语言常用模块与综合系统设计实例精讲

--    File Name:  txmit.vhd
--      Version:  1.1
--         Date:  January 22, 2000
--        Model:  Transmitter Chip
--
--      Company:  Xilinx
--
--
--   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--                Copyright (c) 2000 Xilinx, Inc.
--                All rights reserved

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;

entity txmit is
port (rst,clk16x,wrn : in std_logic ;
	din : in std_logic_vector(7 downto 0) ;
	tdempty : out std_logic ;
	tsre : out std_logic ;
	sdo  : out std_logic 
) ;
end txmit ;

architecture v1 of txmit is
signal tbr : std_logic_vector (7 downto 0) ;
signal fsm :  unsigned (1 downto 0) ;
signal clk1x :  std_logic ;
signal cnt :  unsigned (3 downto 0) ;
signal sdcnt :  unsigned (3 downto 0) ;

begin

process (rst,wrn,clk16x)
begin
	if rst = '1'or wrn='0'then
		tdempty <= '0' ;
		cnt<="0000";
		sdcnt<="0000";
		tbr <= din ;
		fsm<="00";
		sdo<='1';
	elsif clk16x'event and clk16x = '1' then
		if(std_logic_vector(fsm)="00")then --transmit start bit.
			sdo<='0';--start bit.
			cnt<=cnt+"0001";
			if(std_logic_vector(cnt)="1111")then
				fsm<="01";									
			end if;
		 elsif(std_logic_vector(fsm)="01")then --transmit data bit.
		 	cnt<=cnt+"0001";
		 	if(std_logic_vector(cnt)="0000")then
				tbr <= '0' & tbr(7 downto 1);--LSB   
				sdo <= tbr(0) ;
				sdcnt<=sdcnt+"0001";
			end if;
			if(std_logic_vector(sdcnt)="1000")and (std_logic_vector(cnt)="1111")then --8 bits transmit over.
				sdcnt<="0000";
				fsm<="10";
			end if;
		 elsif(std_logic_vector(fsm)="10")then --transmit stop bit.
		 	sdo<='1';
			cnt<=cnt+"0001";
		 	if(std_logic_vector(cnt)="0000")then
				sdcnt<=sdcnt+"0001";
			end if;
			if(std_logic_vector(sdcnt)="0001")and (std_logic_vector(cnt)="0000")then				
				tdempty <= '1' ; -- transmit over.	and fsm will be reset by wrn.
			end if;
		 end if;
	end if;
end process ;
clk1x<=cnt(3);
end ;