top.vhf

51单片机C语言常用模块与综合系统设计实例精讲

                CLR=>CLR,
                D=>D(5),
                Q=>Q(5));
   
   Q6 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(6),
                Q=>Q(6));
   
   Q7 : FDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>D(7),
                Q=>Q(7));
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity BUFT8_MXILINX_top is
   port ( I : in    std_logic_vector (7 downto 0); 
          T : in    std_logic; 
          O : out   std_logic_vector (7 downto 0));
end BUFT8_MXILINX_top;

architecture BEHAVIORAL of BUFT8_MXILINX_top is
   attribute BOX_TYPE   : string ;
   component BUFT
      port ( I : in    std_logic; 
             T : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of BUFT : component is "BLACK_BOX";
   
begin
   I_36_30 : BUFT
      port map (I=>I(0),
                T=>T,
                O=>O(0));
   
   I_36_31 : BUFT
      port map (I=>I(1),
                T=>T,
                O=>O(1));
   
   I_36_32 : BUFT
      port map (I=>I(2),
                T=>T,
                O=>O(2));
   
   I_36_33 : BUFT
      port map (I=>I(3),
                T=>T,
                O=>O(3));
   
   I_36_34 : BUFT
      port map (I=>I(7),
                T=>T,
                O=>O(7));
   
   I_36_35 : BUFT
      port map (I=>I(6),
                T=>T,
                O=>O(6));
   
   I_36_36 : BUFT
      port map (I=>I(5),
                T=>T,
                O=>O(5));
   
   I_36_37 : BUFT
      port map (I=>I(4),
                T=>T,
                O=>O(4));
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity top is
   port ( ADDR : in    std_logic_vector (7 downto 0); 
          INT0 : in    std_logic; 
          INT1 : in    std_logic; 
          INT2 : in    std_logic; 
          INT3 : in    std_logic; 
          INT4 : in    std_logic; 
          INT5 : in    std_logic; 
          INT6 : in    std_logic; 
          INT7 : in    std_logic; 
          RD   : in    std_logic; 
          RST  : in    std_logic; 
          WR   : in    std_logic; 
          TINT : out   std_logic; 
          DATA : inout std_logic_vector (7 downto 0));
end top;

architecture BEHAVIORAL of top is
   attribute HU_SET     : string ;
   attribute BOX_TYPE   : string ;
   signal CS0      : std_logic;
   signal CS1      : std_logic;
   signal CS2      : std_logic;
   signal CS3      : std_logic;
   signal CS4      : std_logic;
   signal CS5      : std_logic;
   signal CS6      : std_logic;
   signal CS7      : std_logic;
   signal CS8      : std_logic;
   signal CS9      : std_logic;
   signal CS10     : std_logic;
   signal CS11     : std_logic;
   signal CS12     : std_logic;
   signal CS13     : std_logic;
   signal CS14     : std_logic;
   signal CS15     : std_logic;
   signal DIN      : std_logic_vector (7 downto 0);
   signal DOUT     : std_logic_vector (7 downto 0);
   signal ENA      : std_logic_vector (7 downto 0);
   signal INTER    : std_logic_vector (7 downto 0);
   signal MINT     : std_logic_vector (7 downto 0);
   signal XLXN_25  : std_logic;
   signal XLXN_206 : std_logic;
   signal XLXN_271 : std_logic;
   signal XLXN_303 : std_logic;
   signal XLXN_309 : std_logic;
   signal XLXN_314 : std_logic;
   signal XLXN_345 : std_logic;
   signal XLXN_347 : std_logic;
   signal XLXN_386 : std_logic;
   signal XLXN_388 : std_logic;
   signal XLXN_393 : std_logic;
   signal XLXN_395 : std_logic;
   signal XLXN_400 : std_logic;
   signal XLXN_402 : std_logic;
   signal XLXN_407 : std_logic;
   signal XLXN_409 : std_logic;
   signal XLXN_414 : std_logic;
   signal XLXN_416 : std_logic;
   signal XLXN_421 : std_logic;
   signal XLXN_423 : std_logic;
   signal XLXN_482 : std_logic;
   signal XLXN_603 : std_logic;
   component IBUF8_MXILINX_top
      port ( I : in    std_logic_vector (7 downto 0); 
             O : out   std_logic_vector (7 downto 0));
   end component;
   
   component OBUFE8_MXILINX_top
      port ( E : in    std_logic; 
             I : in    std_logic_vector (7 downto 0); 
             O : out   std_logic_vector (7 downto 0));
   end component;
   
   component D4_16E_MXILINX_top
      port ( A0  : in    std_logic; 
             A1  : in    std_logic; 
             A2  : in    std_logic; 
             A3  : in    std_logic; 
             E   : in    std_logic; 
             D0  : out   std_logic; 
             D1  : out   std_logic; 
             D10 : out   std_logic; 
             D11 : out   std_logic; 
             D12 : out   std_logic; 
             D13 : out   std_logic; 
             D14 : out   std_logic; 
             D15 : out   std_logic; 
             D2  : out   std_logic; 
             D3  : out   std_logic; 
             D4  : out   std_logic; 
             D5  : out   std_logic; 
             D6  : out   std_logic; 
             D7  : out   std_logic; 
             D8  : out   std_logic; 
             D9  : out   std_logic);
   end component;
   
   component BUFT8_MXILINX_top
      port ( I : in    std_logic_vector (7 downto 0); 
             T : in    std_logic; 
             O : out   std_logic_vector (7 downto 0));
   end component;
   
   component INV
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : component is "BLACK_BOX";
   
   component OR3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR3 : component is "BLACK_BOX";
   
   component AND2B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
   
   component FDCE
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
   
   component VCC
      port ( P : out   std_logic);
   end component;
   attribute BOX_TYPE of VCC : component is "BLACK_BOX";
   
   component OR3B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR3B1 : component is "BLACK_BOX";
   
   component FD8CE_MXILINX_top
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic_vector (7 downto 0); 
             Q   : out   std_logic_vector (7 downto 0));
   end component;
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
   
   component OR8_MXILINX_top
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             I4 : in    std_logic; 
             I5 : in    std_logic; 
             I6 : in    std_logic; 
             I7 : in    std_logic; 
             O  : out   std_logic);
   end component;
   
   attribute HU_SET of XLXI_5 : label is "XLXI_5_15";
   attribute HU_SET of XLXI_6 : label is "XLXI_6_14";
   attribute HU_SET of XLXI_69 : label is "XLXI_69_13";
   attribute HU_SET of XLXI_76 : label is "XLXI_76_9";
   attribute HU_SET of XLXI_97 : label is "XLXI_97_8";
   attribute HU_SET of XLXI_174 : label is "XLXI_174_11";
   attribute HU_SET of XLXI_180 : label is "XLXI_180_10";
   attribute HU_SET of XLXI_193 : label is "XLXI_193_12";
begin
   XLXI_5 : IBUF8_MXILINX_top
      port map (I(7 downto 0)=>DATA(7 downto 0),
                O(7 downto 0)=>DIN(7 downto 0));
   
   XLXI_6 : OBUFE8_MXILINX_top
      port map (E=>XLXN_25,
                I(7 downto 0)=>DOUT(7 downto 0),
                O(7 downto 0)=>DATA(7 downto 0));
   
   XLXI_69 : D4_16E_MXILINX_top
      port map (A0=>ADDR(0),
                A1=>ADDR(1),
                A2=>ADDR(2),
                A3=>ADDR(3),
                E=>ADDR(7),
                D0=>CS0,
                D1=>CS1,
                D2=>CS2,
                D3=>CS3,
                D4=>CS4,
                D5=>CS5,
                D6=>CS6,
                D7=>CS7,
                D8=>CS8,
                D9=>CS9,
                D10=>CS10,
                D11=>CS11,
                D12=>CS12,
                D13=>CS13,
                D14=>CS14,
                D15=>CS15);
   
   XLXI_76 : BUFT8_MXILINX_top
      port map (I(7 downto 0)=>ENA(7 downto 0),
                T=>XLXN_206,
                O(7 downto 0)=>DOUT(7 downto 0));
   
   XLXI_77 : INV
      port map (I=>CS0,
                O=>XLXN_206);
   
   XLXI_97 : BUFT8_MXILINX_top
      port map (I(7 downto 0)=>INTER(7 downto 0),
                T=>XLXN_271,
                O(7 downto 0)=>DOUT(7 downto 0));
   
   XLXI_98 : INV
      port map (I=>CS1,
                O=>XLXN_271);
   
   XLXI_106 : OR3
      port map (I0=>CS0,
                I1=>CS1,
                I2=>CS2,
                O=>XLXN_303);
   
   XLXI_107 : AND2B1
      port map (I0=>RD,
                I1=>XLXN_303,
                O=>XLXN_25);
   
   XLXI_109 : FDCE
      port map (C=>INT0,
                CE=>XLXN_309,
                CLR=>XLXN_314,
                D=>XLXN_309,
                Q=>INTER(0));
   
   XLXI_110 : VCC
      port map (P=>XLXN_309);
   
   XLXI_111 : OR3B1
      port map (I0=>WR,
                I1=>DIN(0),
                I2=>CS8,
                O=>XLXN_314);
   
   XLXI_124 : FDCE
      port map (C=>INT1,
                CE=>XLXN_345,
                CLR=>XLXN_347,
                D=>XLXN_345,
                Q=>INTER(1));
   
   XLXI_125 : VCC
      port map (P=>XLXN_345);
   
   XLXI_126 : OR3B1
      port map (I0=>WR,
                I1=>DIN(0),
                I2=>CS9,
                O=>XLXN_347);
   
   XLXI_140 : FDCE
      port map (C=>INT2,
                CE=>XLXN_386,
                CLR=>XLXN_388,
                D=>XLXN_386,
                Q=>INTER(2));
   
   XLXI_141 : VCC
      port map (P=>XLXN_386);
   
   XLXI_142 : OR3B1
      port map (I0=>WR,
                I1=>DIN(0),
                I2=>CS10,
                O=>XLXN_388);
   
   XLXI_143 : FDCE
      port map (C=>INT3,
                CE=>XLXN_393,
                CLR=>XLXN_395,
                D=>XLXN_393,
                Q=>INTER(3));
   
   XLXI_144 : VCC
      port map (P=>XLXN_393);
   
   XLXI_145 : OR3B1
      port map (I0=>WR,
                I1=>DIN(0),
                I2=>CS11,
                O=>XLXN_395);
   
   XLXI_146 : FDCE
      port map (C=>INT4,
                CE=>XLXN_400,
                CLR=>XLXN_402,
                D=>XLXN_400,
                Q=>INTER(4));
   
   XLXI_147 : VCC
      port map (P=>XLXN_400);
   
   XLXI_148 : OR3B1
      port map (I0=>WR,
                I1=>DIN(0),
                I2=>CS12,
                O=>XLXN_402);
   
   XLXI_149 : FDCE
      port map (C=>INT5,
                CE=>XLXN_407,
                CLR=>XLXN_409,
                D=>XLXN_407,
                Q=>INTER(5));
   
   XLXI_150 : VCC
      port map (P=>XLXN_407);
   
   XLXI_151 : OR3B1
      port map (I0=>WR,
                I1=>DIN(0),
                I2=>CS13,
                O=>XLXN_409);
   
   XLXI_152 : FDCE
      port map (C=>INT6,
                CE=>XLXN_414,
                CLR=>XLXN_416,
                D=>XLXN_414,
                Q=>INTER(6));
   
   XLXI_153 : VCC
      port map (P=>XLXN_414);
   
   XLXI_154 : OR3B1
      port map (I0=>WR,
                I1=>DIN(0),
                I2=>CS14,
                O=>XLXN_416);
   
   XLXI_155 : FDCE
      port map (C=>INT7,
                CE=>XLXN_421,
                CLR=>XLXN_423,
                D=>XLXN_421,
                Q=>INTER(7));
   
   XLXI_156 : VCC
      port map (P=>XLXN_421);
   
   XLXI_157 : OR3B1
      port map (I0=>WR,
                I1=>DIN(0),
                I2=>CS15,
                O=>XLXN_423);
   
   XLXI_174 : FD8CE_MXILINX_top
      port map (C=>WR,
                CE=>CS0,
                CLR=>RST,
                D(7 downto 0)=>DIN(7 downto 0),
                Q(7 downto 0)=>ENA(7 downto 0));
   
   XLXI_180 : BUFT8_MXILINX_top
      port map (I(7 downto 0)=>MINT(7 downto 0),
                T=>XLXN_482,
                O(7 downto 0)=>DOUT(7 downto 0));
   
   XLXI_181 : INV
      port map (I=>CS2,
                O=>XLXN_482);
   
   XLXI_185 : AND2
      port map (I0=>ENA(0),
                I1=>INTER(0),
                O=>MINT(0));
   
   XLXI_186 : AND2
      port map (I0=>ENA(1),
                I1=>INTER(1),
                O=>MINT(1));
   
   XLXI_187 : AND2
      port map (I0=>ENA(2),
                I1=>INTER(2),
                O=>MINT(2));
   
   XLXI_188 : AND2
      port map (I0=>ENA(3),
                I1=>INTER(3),
                O=>MINT(3));
   
   XLXI_189 : AND2
      port map (I0=>ENA(4),
                I1=>INTER(4),
                O=>MINT(4));
   
   XLXI_190 : AND2
      port map (I0=>ENA(5),
                I1=>INTER(5),
                O=>MINT(5));
   
   XLXI_191 : AND2
      port map (I0=>ENA(6),
                I1=>INTER(6),
                O=>MINT(6));
   
   XLXI_192 : AND2
      port map (I0=>ENA(7),
                I1=>INTER(7),
                O=>MINT(7));
   
   XLXI_193 : OR8_MXILINX_top
      port map (I0=>MINT(7),
                I1=>MINT(6),
                I2=>MINT(5),
                I3=>MINT(4),
                I4=>MINT(3),
                I5=>MINT(2),
                I6=>MINT(1),
                I7=>MINT(0),
                O=>XLXN_603);
   
   XLXI_207 : INV
      port map (I=>XLXN_603,
                O=>TINT);
   
end BEHAVIORAL;