📄 top.vhf
字号:
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1i
-- \ \ Application : sch2vhdl
-- / / Filename : top.vhf
-- /___/ /\ Timestamp : 10/19/2006 16:37:20
-- \ \ / \
-- \___\/\___\
--
--Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family xc9500xl -flat -suppress -w top.sch top.vhf
--Design Name: top
--Device: xc9500xl
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesis and simulted, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity IBUF8_MXILINX_top is
port ( I : in std_logic_vector (7 downto 0);
O : out std_logic_vector (7 downto 0));
end IBUF8_MXILINX_top;
architecture BEHAVIORAL of IBUF8_MXILINX_top is
attribute BOX_TYPE : string ;
component IBUF
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of IBUF : component is "BLACK_BOX";
begin
I_36_30 : IBUF
port map (I=>I(4),
O=>O(4));
I_36_31 : IBUF
port map (I=>I(5),
O=>O(5));
I_36_32 : IBUF
port map (I=>I(6),
O=>O(6));
I_36_33 : IBUF
port map (I=>I(7),
O=>O(7));
I_36_34 : IBUF
port map (I=>I(3),
O=>O(3));
I_36_35 : IBUF
port map (I=>I(2),
O=>O(2));
I_36_36 : IBUF
port map (I=>I(1),
O=>O(1));
I_36_37 : IBUF
port map (I=>I(0),
O=>O(0));
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity OBUFE_MXILINX_top is
port ( E : in std_logic;
I : in std_logic;
O : out std_logic);
end OBUFE_MXILINX_top;
architecture BEHAVIORAL of OBUFE_MXILINX_top is
attribute BOX_TYPE : string ;
signal T : std_logic;
component OBUFT
port ( I : in std_logic;
T : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OBUFT : component is "BLACK_BOX";
component INV
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of INV : component is "BLACK_BOX";
begin
I_36_10 : OBUFT
port map (I=>I,
T=>T,
O=>O);
I_36_12 : INV
port map (I=>E,
O=>T);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity OBUFE8_MXILINX_top is
port ( E : in std_logic;
I : in std_logic_vector (7 downto 0);
O : out std_logic_vector (7 downto 0));
end OBUFE8_MXILINX_top;
architecture BEHAVIORAL of OBUFE8_MXILINX_top is
attribute HU_SET : string ;
component OBUFE_MXILINX_top
port ( E : in std_logic;
I : in std_logic;
O : out std_logic);
end component;
attribute HU_SET of I_36_30 : label is "I_36_30_6";
attribute HU_SET of I_36_31 : label is "I_36_31_5";
attribute HU_SET of I_36_32 : label is "I_36_32_4";
attribute HU_SET of I_36_33 : label is "I_36_33_3";
attribute HU_SET of I_36_34 : label is "I_36_34_7";
attribute HU_SET of I_36_35 : label is "I_36_35_0";
attribute HU_SET of I_36_36 : label is "I_36_36_1";
attribute HU_SET of I_36_37 : label is "I_36_37_2";
begin
I_36_30 : OBUFE_MXILINX_top
port map (E=>E,
I=>I(0),
O=>O(0));
I_36_31 : OBUFE_MXILINX_top
port map (E=>E,
I=>I(1),
O=>O(1));
I_36_32 : OBUFE_MXILINX_top
port map (E=>E,
I=>I(2),
O=>O(2));
I_36_33 : OBUFE_MXILINX_top
port map (E=>E,
I=>I(3),
O=>O(3));
I_36_34 : OBUFE_MXILINX_top
port map (E=>E,
I=>I(7),
O=>O(7));
I_36_35 : OBUFE_MXILINX_top
port map (E=>E,
I=>I(6),
O=>O(6));
I_36_36 : OBUFE_MXILINX_top
port map (E=>E,
I=>I(5),
O=>O(5));
I_36_37 : OBUFE_MXILINX_top
port map (E=>E,
I=>I(4),
O=>O(4));
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity D4_16E_MXILINX_top is
port ( A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
E : in std_logic;
D0 : out std_logic;
D1 : out std_logic;
D2 : out std_logic;
D3 : out std_logic;
D4 : out std_logic;
D5 : out std_logic;
D6 : out std_logic;
D7 : out std_logic;
D8 : out std_logic;
D9 : out std_logic;
D10 : out std_logic;
D11 : out std_logic;
D12 : out std_logic;
D13 : out std_logic;
D14 : out std_logic;
D15 : out std_logic);
end D4_16E_MXILINX_top;
architecture BEHAVIORAL of D4_16E_MXILINX_top is
attribute BOX_TYPE : string ;
component AND5B3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND5B3 : component is "BLACK_BOX";
component AND5B2
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND5B2 : component is "BLACK_BOX";
component AND5B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND5B1 : component is "BLACK_BOX";
component AND5
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND5 : component is "BLACK_BOX";
component AND5B4
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND5B4 : component is "BLACK_BOX";
begin
I_36_53 : AND5B3
port map (I0=>A0,
I1=>A1,
I2=>A2,
I3=>A3,
I4=>E,
O=>D8);
I_36_54 : AND5B2
port map (I0=>A1,
I1=>A2,
I2=>E,
I3=>A3,
I4=>A0,
O=>D9);
I_36_55 : AND5B2
port map (I0=>A0,
I1=>A2,
I2=>E,
I3=>A3,
I4=>A1,
O=>D10);
I_36_56 : AND5B1
port map (I0=>A2,
I1=>A0,
I2=>A1,
I3=>A3,
I4=>E,
O=>D11);
I_36_57 : AND5B2
port map (I0=>A0,
I1=>A1,
I2=>E,
I3=>A3,
I4=>A2,
O=>D12);
I_36_58 : AND5B1
port map (I0=>A1,
I1=>A0,
I2=>A2,
I3=>A3,
I4=>E,
O=>D13);
I_36_59 : AND5B1
port map (I0=>A0,
I1=>A1,
I2=>A2,
I3=>A3,
I4=>E,
O=>D14);
I_36_60 : AND5
port map (I0=>A3,
I1=>A2,
I2=>A1,
I3=>A0,
I4=>E,
O=>D15);
I_36_61 : AND5B2
port map (I0=>A3,
I1=>A0,
I2=>E,
I3=>A2,
I4=>A1,
O=>D6);
I_36_62 : AND5B1
port map (I0=>A3,
I1=>A2,
I2=>A1,
I3=>A0,
I4=>E,
O=>D7);
I_36_63 : AND5B2
port map (I0=>A3,
I1=>A1,
I2=>E,
I3=>A2,
I4=>A0,
O=>D5);
I_36_64 : AND5B3
port map (I0=>A0,
I1=>A1,
I2=>A3,
I3=>A2,
I4=>E,
O=>D4);
I_36_65 : AND5B2
port map (I0=>A2,
I1=>A3,
I2=>E,
I3=>A0,
I4=>A1,
O=>D3);
I_36_66 : AND5B3
port map (I0=>A0,
I1=>A3,
I2=>A2,
I3=>A1,
I4=>E,
O=>D2);
I_36_67 : AND5B3
port map (I0=>A1,
I1=>A2,
I2=>A3,
I3=>A0,
I4=>E,
O=>D1);
I_36_68 : AND5B4
port map (I0=>A3,
I1=>A2,
I2=>A1,
I3=>A0,
I4=>E,
O=>D0);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity OR8_MXILINX_top is
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic;
I6 : in std_logic;
I7 : in std_logic;
O : out std_logic);
end OR8_MXILINX_top;
architecture BEHAVIORAL of OR8_MXILINX_top is
attribute BOX_TYPE : string ;
signal S0 : std_logic;
signal S1 : std_logic;
component OR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
component OR4
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR4 : component is "BLACK_BOX";
begin
I_36_94 : OR2
port map (I0=>S0,
I1=>S1,
O=>O);
I_36_95 : OR4
port map (I0=>I4,
I1=>I5,
I2=>I6,
I3=>I7,
O=>S1);
I_36_112 : OR4
port map (I0=>I0,
I1=>I1,
I2=>I2,
I3=>I3,
O=>S0);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FD8CE_MXILINX_top is
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic_vector (7 downto 0);
Q : out std_logic_vector (7 downto 0));
end FD8CE_MXILINX_top;
architecture BEHAVIORAL of FD8CE_MXILINX_top is
attribute BOX_TYPE : string ;
component FDCE
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
begin
Q0 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(0),
Q=>Q(0));
Q1 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(1),
Q=>Q(1));
Q2 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(2),
Q=>Q(2));
Q3 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(3),
Q=>Q(3));
Q4 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(4),
Q=>Q(4));
Q5 : FDCE
port map (C=>C,
CE=>CE,
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -