adecode.vhd

51单片机C语言常用模块与综合系统设计实例精讲

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ADECODE is
    Port ( ADRES : in std_logic_vector(15 downto 0);
           WR  : in std_logic;
           RD  : in std_logic;
           RCS : out std_logic;
           FCS : out std_logic;
           MCS : out std_logic;
           BYCS: out std_logic;
           BSCS: out std_logic;
           LEDCS:out std_logic;
           DIEN: out std_logic;
           MWR : out std_logic;
           MRD : out std_logic;
           REV : out std_logic);
end ADECODE;

architecture Behavioral of ADECODE is

begin
PROCESS(ADRES)
BEGIN
    IF(ADRES>=X"0000" AND ADRES<=X"9EFF")THEN
        IF(WR='0' OR RD='0')THEN
            DIEN<='1';
            MRD<=RD;
            MWR<=WR;
        ELSE
            MRD<='0';
            MWR<='1';
            DIEN<='0';
		  END IF;
    ELSE
        MRD<='0';
        MWR<='1';
        DIEN<='0';
    END IF;
    IF(ADRES>=X"A000" AND ADRES<=X"BFFF")THEN
        RCS<='0';
    ELSE
        RCS<='1';
    END IF;
    IF(ADRES>=X"C000" AND ADRES<=X"FFFF")THEN
        FCS<='0';
    ELSE
        FCS<='1';
    END IF;
    IF(ADRES>=X"9F00" AND ADRES<=X"9F01")THEN
        MCS<='0';
    ELSE
        MCS<='1';
    END IF;
    IF(ADRES=X"9F02")THEN
        BYCS<='0';
    ELSE
        BYCS<='1';
    END IF;
    IF(ADRES=X"9F03")THEN
        BSCS<='0';
    ELSE
        BSCS<='1';
    END IF;
    IF(ADRES=X"9F04")THEN
        LEDCS<='0';
    ELSE
        LEDCS<='1';
    END IF;
    REV<='0';
END PROCESS;

end Behavioral;