top.syr

51单片机C语言常用模块与综合系统设计实例精讲

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "top"
Output Format                      : NGC
Target Device                      : xc9500xl

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : top.lso
verilog2001                        : YES
safe_implementation                : No
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/IBUF8_MXILINX_TOP is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/IBUF8_MXILINX_TOP/BEHAVIORAL is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/OBUFE_MXILINX_TOP is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/OBUFE_MXILINX_TOP/BEHAVIORAL is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/OBUFE8_MXILINX_TOP is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/OBUFE8_MXILINX_TOP/BEHAVIORAL is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/D4_16E_MXILINX_TOP is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/D4_16E_MXILINX_TOP/BEHAVIORAL is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/OR8_MXILINX_TOP is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/OR8_MXILINX_TOP/BEHAVIORAL is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/FD8CE_MXILINX_TOP is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/FD8CE_MXILINX_TOP/BEHAVIORAL is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/BUFT8_MXILINX_TOP is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/BUFT8_MXILINX_TOP/BEHAVIORAL is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/TOP is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
WARNING:HDLParsers:3215 - Unit work/TOP/BEHAVIORAL is now defined in a different file: was D:/C51_BOOK/开始修改/Interrupt/CPLD/IOPORT/top.vhf, now is D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf
Compiling vhdl file "D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf" in Library work.
Entity <ibuf8_mxilinx_top> compiled.
Entity <ibuf8_mxilinx_top> (Architecture <behavioral>) compiled.
Entity <obufe_mxilinx_top> compiled.
Entity <obufe_mxilinx_top> (Architecture <behavioral>) compiled.
Entity <obufe8_mxilinx_top> compiled.
Entity <obufe8_mxilinx_top> (Architecture <behavioral>) compiled.
Entity <d4_16e_mxilinx_top> compiled.
Entity <d4_16e_mxilinx_top> (Architecture <behavioral>) compiled.
Entity <or8_mxilinx_top> compiled.
Entity <or8_mxilinx_top> (Architecture <behavioral>) compiled.
Entity <fd8ce_mxilinx_top> compiled.
Entity <fd8ce_mxilinx_top> (Architecture <behavioral>) compiled.
Entity <buft8_mxilinx_top> compiled.
Entity <buft8_mxilinx_top> (Architecture <behavioral>) compiled.
Entity <top> compiled.
Entity <top> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavioral>).
    Set user-defined property "HU_SET =  XLXI_5_15" for instance <XLXI_5> in unit <top>.
    Set user-defined property "HU_SET =  XLXI_6_14" for instance <XLXI_6> in unit <top>.
    Set user-defined property "HU_SET =  XLXI_69_13" for instance <XLXI_69> in unit <top>.
    Set user-defined property "HU_SET =  XLXI_76_9" for instance <XLXI_76> in unit <top>.
    Set user-defined property "HU_SET =  XLXI_97_8" for instance <XLXI_97> in unit <top>.
    Set user-defined property "HU_SET =  XLXI_174_11" for instance <XLXI_174> in unit <top>.
    Set user-defined property "HU_SET =  XLXI_180_10" for instance <XLXI_180> in unit <top>.
    Set user-defined property "HU_SET =  XLXI_193_12" for instance <XLXI_193> in unit <top>.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <IBUF8_MXILINX_top> (Architecture <behavioral>).
Entity <IBUF8_MXILINX_top> analyzed. Unit <IBUF8_MXILINX_top> generated.

Analyzing Entity <OBUFE8_MXILINX_top> (Architecture <behavioral>).
    Set user-defined property "HU_SET =  I_36_30_6" for instance <I_36_30> in unit <OBUFE8_MXILINX_top>.
    Set user-defined property "HU_SET =  I_36_31_5" for instance <I_36_31> in unit <OBUFE8_MXILINX_top>.
    Set user-defined property "HU_SET =  I_36_32_4" for instance <I_36_32> in unit <OBUFE8_MXILINX_top>.
    Set user-defined property "HU_SET =  I_36_33_3" for instance <I_36_33> in unit <OBUFE8_MXILINX_top>.
    Set user-defined property "HU_SET =  I_36_34_7" for instance <I_36_34> in unit <OBUFE8_MXILINX_top>.
    Set user-defined property "HU_SET =  I_36_35_0" for instance <I_36_35> in unit <OBUFE8_MXILINX_top>.
    Set user-defined property "HU_SET =  I_36_36_1" for instance <I_36_36> in unit <OBUFE8_MXILINX_top>.
    Set user-defined property "HU_SET =  I_36_37_2" for instance <I_36_37> in unit <OBUFE8_MXILINX_top>.
Entity <OBUFE8_MXILINX_top> analyzed. Unit <OBUFE8_MXILINX_top> generated.

Analyzing Entity <OBUFE_MXILINX_top> (Architecture <behavioral>).
Entity <OBUFE_MXILINX_top> analyzed. Unit <OBUFE_MXILINX_top> generated.

Analyzing Entity <D4_16E_MXILINX_top> (Architecture <behavioral>).
Entity <D4_16E_MXILINX_top> analyzed. Unit <D4_16E_MXILINX_top> generated.

Analyzing Entity <BUFT8_MXILINX_top> (Architecture <behavioral>).
Entity <BUFT8_MXILINX_top> analyzed. Unit <BUFT8_MXILINX_top> generated.

Analyzing Entity <FD8CE_MXILINX_top> (Architecture <behavioral>).
Entity <FD8CE_MXILINX_top> analyzed. Unit <FD8CE_MXILINX_top> generated.

Analyzing Entity <OR8_MXILINX_top> (Architecture <behavioral>).
Entity <OR8_MXILINX_top> analyzed. Unit <OR8_MXILINX_top> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <OBUFE_MXILINX_top>.
    Related source file is "D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf".
Unit <OBUFE_MXILINX_top> synthesized.


Synthesizing Unit <OR8_MXILINX_top>.
    Related source file is "D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf".
Unit <OR8_MXILINX_top> synthesized.


Synthesizing Unit <FD8CE_MXILINX_top>.
    Related source file is "D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf".
Unit <FD8CE_MXILINX_top> synthesized.


Synthesizing Unit <BUFT8_MXILINX_top>.
    Related source file is "D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf".
Unit <BUFT8_MXILINX_top> synthesized.


Synthesizing Unit <D4_16E_MXILINX_top>.
    Related source file is "D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf".
Unit <D4_16E_MXILINX_top> synthesized.


Synthesizing Unit <OBUFE8_MXILINX_top>.
    Related source file is "D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf".
Unit <OBUFE8_MXILINX_top> synthesized.


Synthesizing Unit <IBUF8_MXILINX_top>.
    Related source file is "D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf".
Unit <IBUF8_MXILINX_top> synthesized.


Synthesizing Unit <top>.
    Related source file is "D:/C51_BOOK/开始修改/Interrupt/CPLD/Interrupt/top.vhf".
WARNING:Xst:647 - Input <ADDR<6:4>> is never used.
WARNING:Xst:646 - Signal <CS3> is assigned but never used.
WARNING:Xst:646 - Signal <CS4> is assigned but never used.
WARNING:Xst:646 - Signal <CS5> is assigned but never used.
WARNING:Xst:646 - Signal <CS6> is assigned but never used.
WARNING:Xst:646 - Signal <CS7> is assigned but never used.
Unit <top> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <top> ...

Optimizing unit <IBUF8_MXILINX_top> ...

Optimizing unit <D4_16E_MXILINX_top> ...

Optimizing unit <BUFT8_MXILINX_top> ...

Optimizing unit <FD8CE_MXILINX_top> ...

Optimizing unit <OR8_MXILINX_top> ...

Optimizing unit <OBUFE_MXILINX_top> ...

Optimizing unit <OBUFE8_MXILINX_top> ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : xc9500xl
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 28

Cell Usage :
# BELS                             : 33
#      AND2                        : 8
#      AND5                        : 1
#      INV                         : 12
#      OR2                         : 1
#      OR3                         : 1
#      OR4                         : 2
#      VCC                         : 8
# FlipFlops/Latches                : 16
#      FDCE                        : 16
# Tri-States                       : 24
#      BUFT                        : 24
# IO Buffers                       : 33
#      IBUF                        : 24
#      OBUF                        : 1
#      OBUFT                       : 8
# Others                           : 24
#      AND2B1                      : 1
#      AND5B1                      : 4
#      AND5B2                      : 6
#      AND5B3                      : 4
#      AND5B4                      : 1
#      OR3B1                       : 8
=========================================================================
CPU : 8.05 / 10.26 s | Elapsed : 8.00 / 9.00 s
 
--> 

Total memory usage is 69200 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   22 (   0 filtered)
Number of infos    :    0 (   0 filtered)